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Dominique Borrione Vis

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*2009
49EEYann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic: MYGEN: automata-based on-line test generator for assertion-based verification. ACM Great Lakes Symposium on VLSI 2009: 75-80
48EEFlorent Ouchet, Dominique Borrione, Katell Morin-Allory, Laurence Pierre: High-level symbolic simulation for automatic model extraction. DDECS 2009: 218-221
2008
47EEYann Oddos, Katell Morin-Allory, Dominique Borrione: Assertion-Based Design with Horus. MEMOCODE 2008: 75-76
46EEDominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz: Executable formal specification and validation of NoC communication infrastructures. SBCCI 2008: 176-181
45EEJulien Schmaltz, Dominique Borrione: A functional formalization of on chip communications. Formal Asp. Comput. 20(3): 241-258 (2008)
2007
44 Yann Oddos, Katell Morin-Allory, Dominique Borrione: Prototyping Generators for On-line Test Vector Generation Based on PSL Properties. DDECS 2007: 383-388
43EEKatell Morin-Allory, Laurent Fesquet, Benjamin Roustan, Dominique Borrione: Asynchronous online-monitoring of logical and temporal assertions. FDL 2007: 286-290
42EEDominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz: A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study. NOCS 2007: 127-136
41EEKatell Morin-Allory, Eric Gascard, Dominique Borrione: Synthesis of Property Monitors for Online Fault Detection. Journal of Circuits, Systems, and Computers 16(6): 943-960 (2007)
2006
40EEJulien Schmaltz, Dominique Borrione: Towards a formal theory of on chip communications in the ACL2 logic. ACL2 2006: 47-56
39EEKatell Morin-Allory, Dominique Borrione: Proven correct monitors from PSL specifications. DATE 2006: 1246-1251
38EEKatell Morin-Allory, Dominique Borrione: On-line Monitoring of Properties Built on Regular Expressions. FDL 2006: 249-255
37EEKatell Morin-Allory, Laurent Fesquet, Dominique Borrione: Asynchronous Assertion Monitors for multi-Clock Domain System Verification. IEEE International Workshop on Rapid System Prototyping 2006: 98-102
36EEJulien Schmaltz, Dominique Borrione: Formalizing On Chip Communications in a Functional Style. Trustworthy Software 2006
35EEYann Oddos, Katell Morin-Allory, Dominique Borrione: On-Line Test Vector Generation from Temporal Constraints Written in PSL. VLSI-SoC 2006: 397-402
2005
34 Dominique Borrione, Wolfgang J. Paul: Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings Springer 2005
33EEGhiath Al Sammane, Dominique Borrione, Remy Chevallier: Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning. ACM Great Lakes Symposium on VLSI 2005: 260-263
32EEJulien Schmaltz, Dominique Borrione: A Generic Network on Chip Model. TPHOLs 2005: 310-325
31EEDiana Toma, Dominique Borrione: Formal Verification of a SHA-1 Circuit Core Using ACL2. TPHOLs 2005: 326-341
2004
30EEDiana Toma, Dominique Borrione, Ghiath Al Sammane: Combining Several Paradigms for Circuit Validation and Verification. CASSIS 2004: 229-249
29EEJulien Schmaltz, Dominique Borrione: A Functional Approach to the Formal Specification of Networks on Chip. FMCAD 2004: 52-66
28EEGhiath Al Sammane, Julien Schmaltz, Diana Toma, Pierre Ostier, Dominique Borrione: TheoSim: combining symbolic simulation and theorem proving for hardware verification. SBCCI 2004: 60-65
2003
27EEGhiath Al Sammane, Diana Toma, Julien Schmaltz, Pierre Ostier, Dominique Borrione: Constrained Symbolic Simulation with Mathematica and ACL2. CHARME 2003: 150-157
26EEDominique Borrione, Menouer Boubekeur: Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications. FDL 2003: 481-492
25EEDominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Sirianni: An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. HICSS 2003: 279
24EEEmil Dumitrescu, Dominique Borrione: Symbolic Simulation as a Simplifying Strategy for SoC Verification. IWSOC 2003: 378-383
23 Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Sirianni: Validation of asynchronous circuit specifications using IF/CADP. VLSI-SOC 2003: 86-91
2002
22EEJoel Blasquez, Marten van Hulst, Andrea Fedeli, Jean-Luc Lambert, Dominique Borrione, Coby Hanoch, Pierre Bricaud: Formal Verification Techniques: Industrial Status and Perspectives. DATE 2002: 1050-1051
21 Jorgiano Vidal, David Déharbe, Dominique Borrione: Improving Static Ordering of BDDs for Reachability Analysis. IWLS 2002: 73-77
2001
20EES. Reda, Ayman M. Wahba, Ashraf M. Salem, Dominique Borrione, M. Ghonaimy: On the use of don't cares during symbolic reachability analysis. ISCAS (5) 2001: 121-124
2000
19EEDominique Borrione, Julia Dushina, Laurence V. Pierre: A compositional model for the functional verification of high-level synthesis results. IEEE Trans. VLSI Syst. 8(5): 526-530 (2000)
18 Vanderlei Moraes Rodrigues, Dominique Borrione, Philippe Georgelin: Using the ACL2 Theorem Prover to Reason about VHDL Components. RITA 7(1): 129-148 (2000)
1999
17 Raimund Ubar, Dominique Borrione: Design Error Diagnosis in Digital Circuits without Error Model. VLSI 1999: 281-292
1997
16 Dominique Borrione, F. Vestman, H. Bouamama: An approach to Verilog-VHDL interoperability for synchronous designs. CHARME 1997: 65-87
15EEAyman M. Wahba, Dominique Borrione: Connection error location and correction in combinational circuits. ED&TC 1997: 235-241
1996
14 Dominique Borrione, H. Bouamama, David Déharbe, C. Le Faou, Ayman M. Wahba: HDL-Based Integration of Formal Methods and CAD Tools in the PREVAIL Environment. FMCAD 1996: 450-467
13EEAyman M. Wahba, Dominique Borrione: A method for automatic design error location and correction in combinational logic circuits. J. Electronic Testing 8(2): 113-127 (1996)
1995
12 Ayman M. Wahba, Dominique Borrione: Design error diagnosis in sequential circuits. CHARME 1995: 171-188
11 David Déharbe, Dominique Borrione: Semantics of a verification-oriented subset of VHDL. CHARME 1995: 293-310
10 Dominique Borrione, Ashraf M. Salem: Denotational Semantics of a Synchronous VHDL Subset. Formal Methods in System Design 7(1/2): 53-71 (1995)
1994
9EECatherine Bayol, Bernard Soulas, Dominique Borrione, Fulvio Corno, Paolo Prinetto: A process algebra interpretation of a verification oriented overlanguage of VHDL. EURO-DAC 1994: 506-511
1992
8EEDominique Borrione, Laurence V. Pierre, Ashraf M. Salem: Formal Verification of VHDL Descriptions in the Prevail Environment. IEEE Design & Test of Computers 9(2): 42-56 (1992)
7EEDominique Borrione, Robert Piloty, Dwight D. Hill, Karl J. Lieberherr, Philip Moorby: Three Decades of HDLs: Part II, Conlan Through Verilog. IEEE Design & Test of Computers 9(3): 54-63 (1992)
1989
6 Dominique Borrione, Paolo Prinetto: Zero-Defect Designs, Why and How: Formal Verification vs. Automated Synthesis. IFIP Congress 1989: 233-240
1983
5 Robert Piloty, Dominique Borrione, Mario Barbacci, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly: CONLAN Report Springer 1983
1980
4EERobert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly: CONLAN: a formal construction method for hardware description languages: basic principles. AFIPS National Computer Conference 1980: 209-217
3EERobert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly: CONLAN: a formal construction method for hardware description languages: language derivation. AFIPS National Computer Conference 1980: 219-227
2EERobert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly: CONLAN: a formal construction method for hardware description languages: language application. AFIPS National Computer Conference 1980: 229-236
1 Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly: An Overview of CONLAN: A Formal Construction Method for Hardware Description Language. IFIP Congress 1980: 199-204

Coauthor Index

1Mario Barbacci [1] [2] [3] [4] [5]
2Catherine Bayol [9]
3Joel Blasquez [22]
4H. Bouamama [14] [16]
5Menouer Boubekeur [23] [25] [26]
6Marc Boule [49]
7Pierre Bricaud [22]
8Remy Chevallier [33]
9Fulvio Corno [9]
10David Déharbe [11] [14] [21]
11Donald L. Dietmeyer [1] [2] [3] [4] [5]
12Emil Dumitrescu [24] [25]
13Julia Dushina [19]
14C. Le Faou [14]
15Andrea Fedeli [22]
16Laurent Fesquet [37] [43]
17Eric Gascard [41]
18Philippe Georgelin [18]
19M. Ghonaimy [20]
20Coby Hanoch [22]
21Amr Helmy [42] [46]
22Dwight D. Hill [7]
23Fredrick J. Hill [1] [2] [3] [4] [5]
24Marten van Hulst [22]
25Jean-Luc Lambert [22]
26Karl J. Lieberherr [7]
27Philip Moorby [7]
28Katell Morin-Allory [35] [37] [38] [39] [41] [43] [44] [47] [48] [49]
29Laurent Mounier [23]
30Yann Oddos [35] [44] [47] [49]
31Pierre Ostier [27] [28]
32Florent Ouchet [48]
33Wolfgang J. Paul [34]
34Laurence Pierre (Laurence V. Pierre) [8] [19] [42] [46] [48]
35Robert Piloty [1] [2] [3] [4] [5] [7]
36Paolo Prinetto [6] [9]
37S. Reda [20]
38Marc Renaudin [23] [25]
39Jean-Baptiste Rigaud [25]
40Vanderlei Moraes Rodrigues [18]
41Benjamin Roustan [43]
42Ashraf M. Salem [8] [10] [20]
43Ghiath Al Sammane [27] [28] [30] [33]
44Julien Schmaltz [27] [28] [29] [32] [36] [40] [42] [45] [46]
45Antoine Sirianni [23] [25]
46Patrick Skelly [1] [2] [3] [4] [5]
47Bernard Soulas [9]
48Diana Toma [27] [28] [30] [31]
49Raimund Ubar [17]
50F. Vestman [16]
51Jorgiano Vidal [21]
52Ayman M. Wahba [12] [13] [14] [15] [20]
53Zeljko Zilic [49]

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Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)