Yannick Bonhomme Vis

*	2009
12	EE	Valentin Gherman, Samuel Evain, Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme: System-level hardware-based protection of memories against soft-errors. DATE 2009: 1222-1225
11	EE	Richard Buchmann, Mickael Cartron, Yannick Bonhomme: Transaction-based modeling for large scale simulations of heterogeneous systems. SimuTools 2009: 33
	2006
10	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electronic Testing 22(1): 89-99 (2006)
	2005
9	EE	Patrick Girard, Yannick Bonhomme: Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing. J. Low Power Electronics 1(1): 85-95 (2005)
	2004
8	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Design of Routing-Constrained Low Power Scan Chains. DATE 2004: 62-67
7	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Design of Routing-Constrained Low Power Scan Chains. DELTA 2004: 287-294
6	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: Power-Driven Routing-Constrained Scan Chain Design. J. Electronic Testing 20(6): 647-660 (2004)
	2003
5	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC 2003: 488-493
	2002
4	EE	Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Test Power: a Big Issue in Large SOC Designs. DELTA 2002: 447-449
3	EE	Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Power Driven Chaining of Flip-Flops in Scan Architectures. ITC 2002: 796-803
	2001
2	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Asian Test Symposium 2001: 253-258
1	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Gated Clock Scheme for Low Power Scan-Based BIST. IOLTW 2001: 87-89

Coauthor Index

1	Richard Buchmann	[11]
2	Mickael Cartron	[11] [12]
3	Samuel Evain	[12]
4	Valentin Gherman	[12]
5	Patrick Girard	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
6	Loïs Guiller	[1] [2] [5] [6] [7] [8] [10]
7	Christian Landrault	[1] [2] [3] [4] [5] [6] [7] [8] [10]
8	Serge Pravossoudovitch	[1] [2] [3] [4] [5] [6] [7] [8] [10]
9	Nathaniel Seymour	[12]
10	Arnaud Virazel	[7] [8] [10]

Colors in the list of coauthors