David Blaauw

David T. Blaauw

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2008

181 EE Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Stress aware layout optimization. ISPD 2008: 168-174

180 EE Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw: A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 272-285 (2008)

179 EE Sarvesh H. Kulkarni, D. M. Sylvester, David T. Blaauw: Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 481-494 (2008)

178 EE David Blaauw, Kaviraj Chopra, Ashish Srivastava, Louis Scheffer: Statistical Timing Analysis: From Basic Principles to State of the Art. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 589-607 (2008)

2007

177 EE Sanjay Pant, David Blaauw: Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks. ASP-DAC 2007: 757-762

176 EE Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer: Top-k Aggressors Sets in Delay Noise Analysis. DAC 2007: 174-179

175 EE Mingoo Seok, Scott Hanson, Dennis Sylvester, David Blaauw: Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design. DAC 2007: 694-699

174 EE Scott Hanson, Mingoo Seok, Dennis Sylvester, David Blaauw: Nanometer Device Scaling in Subthreshold Circuits. DAC 2007: 700-705

173 EE Gregory K. Chen, David Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim: Yield-driven near-threshold SRAM design. ICCAD 2007: 660-666

172 EE Vivek Joshi, David Blaauw, Dennis Sylvester: Soft-edge flip-flops for improved timing yield: design and optimization. ICCAD 2007: 667-673

171 EE Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada: Victim alignment in crosstalk aware timing analysis. ICCAD 2007: 698-704

170 EE Bo Zhai, Ronald G. Dreslinski, David Blaauw, Trevor N. Mudge, Dennis Sylvester: Energy efficient near-threshold chip multi-processing. ISLPED 2007: 32-37

169 EE Jae-sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, Ram Krishnamurthy: A robust edge encoding technique for energy-efficient multi-cycle interconnect. ISLPED 2007: 68-73

168 EE Jae-sun Seo, Prashant Singh, Dennis Sylvester, David Blaauw: Self-Time Regenerators for High-Speed and Low-Power Interconnect. ISQED 2007: 621-626

167 EE Mini Nanua, David Blaauw: Investigating Crosstalk in Sub-Threshold Circuits. ISQED 2007: 639-646

166 EE Mini Nanua, David Blaauw: Crosstalk Waveform Modeling Using Wave Fitting. PATMOS 2007: 211-221

165 EE Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction CoRR abs/0710.4679: (2007)

164 EE Aseem Agarwal, Kaviraj Chopra, David Blaauw: Statistical Timing Based Optimization using Gate Sizing CoRR abs/0710.4697: (2007)

163 EE Sanjay Pant, Eli Chiprout, David Blaauw: Power Grid Physics and Implications for CAD. IEEE Design & Test of Computers 24(3): 246-254 (2007)

162 EE Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester: Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 468-479 (2007)

2006

161 EE Eric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Reliability modeling and management in dynamic microprocessor-based systems. DAC 2006: 1057-1060

160 EE Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester: An efficient static algorithm for computing the soft error rates of combinational circuits. DATE 2006: 164-169

159 EE Kaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylvester: A new statistical max operation for propagating skewness in statistical timing analysis. ICCAD 2006: 237-243

158 EE Sarvesh H. Kulkarni, Dennis Sylvester, David Blaauw: A statistical framework for post-silicon tuning through body bias clustering. ICCAD 2006: 39-46

157 EE Rajeev R. Rao, David Blaauw, Dennis Sylvester: Soft error reduction in combinational logic using gate resizing and flipflop selection. ICCAD 2006: 502-509

156 EE Brian Cline, Kaviraj Chopra, David Blaauw, Yu Cao: Analysis and modeling of CD variation for statistical static timing. ICCAD 2006: 60-66

155 EE Sanjay Pant, David Blaauw: An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks. ICCD 2006

154 EE David Blaauw, Bo Zhai: Energy efficient design for subthreshold supply voltage operation. ISCAS 2006

153 EE Scott Hanson, Dennis Sylvester, David Blaauw: A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits. ISLPED 2006: 338-341

152 EE Scott Hanson, Bo Zhai, David Blaauw, Dennis Sylvester, Andres Bryant, Xinlin Wang: Energy optimality and variability in subthreshold design. ISLPED 2006: 363-365

151 EE Vivek Joshi, Rajeev R. Rao, David Blaauw, Dennis Sylvester: Logic SER Reduction through Flipflop Redesign. ISQED 2006: 611-616

150 EE Mini Nanua, David Blaauw: Receiver Modeling for Static Functional Crosstalk Analysis. PATMOS 2006: 329-339

149 EE Scott Hanson, Bo Zhai, Kerry Bernstein, David Blaauw, Andres Bryant, Leland Chang, Koushik K. Das, Wilfried Haensch, Edward J. Nowak, Dennis Sylvester: Ultralow-voltage, minimum-energy CMOS. IBM Journal of Research and Development 50(4-5): 469-490 (2006)

148 EE Dongwoo Lee, David Blaauw, Dennis Sylvester: Runtime Leakage Minimization Through Probability-Aware Optimization. IEEE Trans. VLSI Syst. 14(10): 1075-1088 (2006)

147 EE Kanak Agarwal, Dennis Sylvester, David Blaauw: Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 892-901 (2006)

146 EE Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David Blaauw: Statistical interconnect metrics for physical-design optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1273-1288 (2006)

145 EE Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Analytical yield prediction considering leakage/performance correlation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1685-1695 (2006)

2005

144 EE Amit Jain, David Blaauw: Slack borrowing in flip-flop based sequential circuits. ACM Great Lakes Symposium on VLSI 2005: 96-101

143 EE Kanak Agarwal, Dennis Sylvester, David Blaauw, Anirudh Devgan: Achieving continuous V_T performance in a dual V_T process. ASP-DAC 2005: 393-398

142 EE David Blaauw, Anirudh Devgan, Farid N. Najm: Leakage power: trends, analysis and avoidance. ASP-DAC 2005

141 EE Todd M. Austin, Valeria Bertacco, David Blaauw, Trevor N. Mudge: Opportunities and challenges for better than worst-case design. ASP-DAC 2005: 2-7

140 EE Dongwoo Lee, David Blaauw, Dennis Sylvester: Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment. ASP-DAC 2005: 399-404

139 EE Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David Blaauw: Statistical modeling of cross-coupling effects in VLSI interconnects. ASP-DAC 2005: 503-506

138 EE Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David Blaauw: A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution. CASES 2005: 249-256

137 EE Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladimir Zolotov: Circuit optimization using statistical static timing analysis. DAC 2005: 321-324

136 EE Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director: Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. DAC 2005: 535-540

135 EE David Blaauw, Kaviraj Chopra: CAD tools for variation tolerance. DAC 2005: 766

134 EE Aseem Agarwal, Kaviraj Chopra, David Blaauw: Statistical Timing Based Optimization using Gate Sizing. DATE 2005: 400-405

133 EE Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction. DATE 2005: 80-85

132 Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David Blaauw, Dennis Sylvester: Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. ICCAD 2005: 1023-1028

131 Sanjay Pant, David Blaauw: Static timing analysis considering power supply variations. ICCAD 2005: 365-371

130 Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David Blaauw, Vladimir Zolotov: Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. ICCAD 2005: 705-712

129 Amit Jain, David Blaauw, Vladimir Zolotov: Accurate delay computation for noisy waveform shapes. ICCAD 2005: 947-953

128 EE Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd M. Austin, David Blaauw: Energy Optimization of Subthreshold-Voltage Sensor Network Processors. ISCA 2005: 197-207

127 EE Eric Karl, Dennis Sylvester, David Blaauw: Timing error correction techniques for voltage-scalable on-chip memories. ISCAS (4) 2005: 3563-3566

126 EE Bo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester: Analysis and mitigation of variability in subthreshold design. ISLPED 2005: 20-25

125 EE Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif: An efficient surface-based low-power buffer insertion algorithm. ISPD 2005: 86-93

124 EE Mini Nanua, David Blaauw, Chanhee Oh: Leakage Current Modeling in PD SOI Circuits. ISQED 2005: 113-117

123 EE Harmander Deogun, Dennis Sylvester, David Blaauw: Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate. ISQED 2005: 175-180

122 EE David Roberts, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner: Error Analysis for the Support of Robust Voltage Scaling. ISQED 2005: 65-70

121 EE Rajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan: Modeling and Analysis of Parametric Yield under Power and Performance Constraints. IEEE Design & Test of Computers 22(4): 376-385 (2005)

120 EE Nam Sung Kim, David Blaauw, Trevor N. Mudge: Quantitative analysis and optimization techniques for on-chip cache leakage power. IEEE Trans. VLSI Syst. 13(10): 1147-1156 (2005)

119 EE Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner: The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. IEEE Trans. VLSI Syst. 13(11): 1239-1252 (2005)

118 EE Rajeev R. Rao, Harmander Deogun, David Blaauw, Dennis Sylvester: Bus encoding for total power reduction using a leakage-aware buffer configuration. IEEE Trans. VLSI Syst. 13(12): 1376-1383 (2005)

117 EE Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: Probability distribution of signal arrival times using Bayesian networks. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1784-1794 (2005)

116 EE Dongwoo Lee, David Blaauw, Dennis Sylvester: Static leakage reduction through simultaneous V/sub t//T/sub ox/ and state assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1014-1029 (2005)

2004

115 EE Kanak Agarwal, Dennis Sylvester, David Blaauw: A simplified transmission-line based crosstalk noise model for on-chip RLC wiring. ASP-DAC 2004: 858-864

114 EE Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: A stochastic approach To power grid analysis. DAC 2004: 171-176

113 EE Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge: Circuit-aware architectural simulation. DAC 2004: 305-310

112 EE Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula: Variational delay metrics for interconnect timing analysis. DAC 2004: 381-384

111 EE Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Parametric yield estimation considering leakage variability. DAC 2004: 442-447

110 EE Aseem Agarwal, Florentin Dartu, David Blaauw: Statistical gate delay model considering multiple input switching. DAC 2004: 658-663

109 EE Dongwoo Lee, Vladimir Zolotov, David Blaauw: Static timing analysis using backward signal propagation. DAC 2004: 664-669

108 EE Ashish Srivastava, Dennis Sylvester, David Blaauw: Statistical optimization of leakage power considering process variations using dual-Vth and sizing. DAC 2004: 773-778

107 EE Harmander Deogun, Rajeev R. Rao, Dennis Sylvester, David Blaauw: Leakage-and crosstalk-aware bus encoding for total power reduction. DAC 2004: 779-782

106 EE Ashish Srivastava, Dennis Sylvester, David Blaauw: Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. DAC 2004: 783-787

105 EE Bo Zhai, David Blaauw, Dennis Sylvester, Krisztián Flautner: Theoretical and practical limits of dynamic voltage scaling. DAC 2004: 868-873

104 EE Dongwoo Lee, Harmander Deogun, David Blaauw, Dennis Sylvester: Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization. DATE 2004: 494-499

103 EE Ashish Srivastava, Dennis Sylvester, David Blaauw: Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design. DATE 2004: 718-719

102 EE Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David Blaauw, Trevor N. Mudge: Reducing pipeline energy demands with local DVS and dynamic retiming. ISLPED 2004: 319-324

101 EE Woo Hyung Lee, Sanjay Pant, David Blaauw: Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids. ISQED 2004: 131-136

100 EE Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner: Making Typical Silicon Matter with Razor. IEEE Computer 37(3): 57-65 (2004)

99 EE Todd M. Austin, David Blaauw, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Wayne Wolf: Mobile Supercomputers. IEEE Computer 37(5): 81-83 (2004)

98 EE Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner: Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. IEEE Micro 24(6): 10-20 (2004)

97 Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical analysis of subthreshold leakage current for VLSI circuits. IEEE Trans. VLSI Syst. 12(2): 131-139 (2004)

96 Dongwoo Lee, David Blaauw, Dennis Sylvester: Gate oxide leakage current analysis and reduction for VLSI circuits. IEEE Trans. VLSI Syst. 12(2): 155-166 (2004)

95 Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge: Circuit and microarchitectural techniques for reducing cache leakage power. IEEE Trans. VLSI Syst. 12(2): 167-184 (2004)

94 EE Kanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driver output model for on-chip RLC transmission lines. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 128-136 (2004)

93 EE Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Postroute gate sizing for crosstalk noise reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1670-1677 (2004)

92 EE Aseem Agarwal, Vladimir Zolotov, David Blaauw: Statistical clock skew analysis considering intradie-process variations. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1231-1242 (2004)

91 EE Kanak Agarwal, Dennis Sylvester, David Blaauw: A simple metric for slew rate of RC circuits based on two circuit moments. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1346-1354 (2004)

2003

90 EE Jan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang: Reshaping EDA for power. DAC 2003: 15

89 EE Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester: Analysis and minimization techniques for total leakage considering gate oxide leakage. DAC 2003: 175-180

88 EE Dongwoo Lee, David Blaauw: Static leakage reduction through simultaneous threshold voltage and state assignment. DAC 2003: 191-194

87 EE Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Computation and Refinement of Statistical Bounds on Circuit Delay. DAC 2003: 348-353

86 EE Kanak Agarwal, Dennis Sylvester, David Blaauw: An effective capacitance based driver output model for on-chip RLC interconnects. DAC 2003: 376-381

85 EE Bhavana Thudi, David Blaauw: Non-iterative switching window computation for delay-noise. DAC 2003: 390-395

84 EE Kanak Agarwal, Dennis Sylvester, David Blaauw: Simple metrics for slew rate of RC circuits based on two circuit moments. DAC 2003: 950-953

83 EE Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Post-route gate sizing for crosstalk noise reduction. DAC 2003: 954-957

82 EE Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical Timing Analysis Using Bounds. DATE 2003: 10062-10067

81 EE D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David Blaauw, Rajendran Panda, Murat R. Becer, A. Ardelea, A. Patel: SOI Transistor Model for Fast Transient Simulation. ICCAD 2003: 120128

80 EE Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: Vectorless Analysis of Supply Noise Induced Delay Variation. ICCAD 2003: 184-192

79 EE Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: AU: Timing Analysis Under Uncertainty. ICCAD 2003: 615-620

78 EE Nam Sung Kim, David Blaauw, Trevor N. Mudge: Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches. ICCAD 2003: 627-632

77 EE Aseem Agarwal, David Blaauw, Vladimir Zolotov: Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations. ICCAD 2003: 900-907

76 EE Aseem Agarwal, David Blaauw, Vladimir Zolotov: Statistical Clock Skew Analysis Considering Intra-Die Process Variations. ICCAD 2003: 914-921

75 EE Shidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester: Optimal Inductance for On-chip RLC Interconnections. ICCD 2003: 264-

74 EE Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) 2003: 668-671

73 EE Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical estimation of leakage current considering inter- and intra-die process variation. ISLPED 2003: 84-89

72 EE Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Post-Route Gate Sizing for Crosstalk Noise Reduction. ISQED 2003: 171-176

71 EE Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester: Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design. ISQED 2003: 287-292

70 EE Chanhee Oh, David Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta: Static Electromigration Analysis for Signal Interconnects. ISQED 2003: 377-

69 EE Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David Blaauw: An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages. ISVLSI 2003: 149-154

68 EE Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge: Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. MICRO 2003: 7-18

67 EE Nam Sung Kim, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan: Leakage Current: Moore's Law Meets Static Power. IEEE Computer 36(12): 68-75 (2003)

66 EE Rajendran Panda, Savithri Sundareswaran, David Blaauw: Impact of Low-Impedance Substrate on Power Supply Integrity. IEEE Design & Test of Computers 20(3): 16-22 (2003)

65 EE David Blaauw, Supamas Sirichotiyakul, Chanhee Oh: Driver modeling and alignment for worst-case delay noise. IEEE Trans. VLSI Syst. 11(2): 157-166 (2003)

64 EE David Blaauw, Chanhee Oh, Vladimir Zolotov, Aurobindo Dasgupta: Static electromigration analysis for on-chip signal interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 39-48 (2003)

63 EE Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 49-66 (2003)

62 EE Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj: Early probabilistic noise estimation for capacitively coupled interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 337-345 (2003)

61 EE Li Ding, David T. Blaauw, Pinaki Mazumder: Accurate crosstalk noise modeling for early signal integrity analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 627-634 (2003)

60 EE David T. Blaauw, Luciano Lavagno: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 962-963 (2003)

59 EE Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul: Probabilistic analysis of interconnect coupling noise. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1188-1203 (2003)

58 EE Aseem Agarwal, Vladimir Zolotov, David T. Blaauw: Statistical timing analysis using bounds and selective enumeration. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1243-1260 (2003)

2002

57 EE Himanshu Kaul, Dennis Sylvester, David Blaauw: Active shields: a new approach to shielding global wires. ACM Great Lakes Symposium on VLSI 2002: 112-117

56 EE Sarma B. K. Vrudhula, David Blaauw, Supamas Sirichotiyakul: Estimation of the likelihood of capacitive coupling noise. DAC 2002: 653-658

55 EE Murat R. Becer, Vladimir Zolotov, David Blaauw, Rajendran Panda, Ibrahim N. Hajj: Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . DATE 2002: 456-464

54 EE Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: A precorrected-FFT method for simulating on-chip inductance. ICCAD 2002: 221-227

53 EE Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: Estimation of signal arrival times in the presence of delay noise. ICCAD 2002: 418-422

52 EE Vladimir Zolotov, David Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy: Noise propagation and failure criteria for VLSI designs. ICCAD 2002: 587-594

51 EE Li Ding, David Blaauw, Pinaki Mazumder: Efficient crosstalk noise modeling using aggressor and tree reductions. ICCAD 2002: 595-600

50 EE Steven M. Martin, Krisztián Flautner, Trevor N. Mudge, David Blaauw: Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. ICCAD 2002: 721-725

49 EE Krisztián Flautner, Nam Sung Kim, Steve Martin, David Blaauw, Trevor N. Mudge: Drowsy Caches: Simple Techniques for Reducing Leakage Power. ISCA 2002: 148-157

48 EE Li Ding, Pinaki Mazumder, David Blaauw: Crosstalk noise estimation using effective coupling capacitance. ISCAS (5) 2002: 645-648

47 EE Ashish Srivastava, Robert Bai, David Blaauw, Dennis Sylvester: Modeling and analysis of leakage power considering within-die process variations. ISLPED 2002: 64-67

46 EE Murat R. Becer, Rajendran Panda, David Blaauw, Ibrahim N. Hajj: Pre-route Noise Estimation in Deep Submicron Integrated Circuits. ISQED 2002: 413-418

45 EE Vladimir Zolotov, David Blaauw, Rajendran Panda, Chanhee Oh: Noise Injection and Propagation in High Performance Designs. ISQED 2002: 425-430

44 EE Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh: False-Noise Analysis Using Resolution Method. ISQED 2002: 437-

43 EE Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge: Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. MICRO 2002: 219-230

42 EE Fadi A. Aloul, Soha Hassoun, Karem A. Sakallah, David Blaauw: Robust SAT-Based Search Algorithm for Leakage Power Reduction. PATMOS 2002: 167-177

41 EE Murat R. Becer, David Blaauw, Ibrahim N. Hajj, Rajendran Panda: Early probabilistic noise estimation for capacitively coupled interconnects. SLIP 2002: 77-83

40 EE Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 16-21

39 EE Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 29-36

38 EE Kanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driving point model for on-chip RLC interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 63-69

37 EE Bhavana Thudi, David Blaauw: Efficient switching window computation for cross-talk noise. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 84-91

36 EE Himanshu Kaul, Dennis Sylvester, David Blaauw: Active shielding of RLC global interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 98-104

35 EE Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov: False-noise analysis using logic implications. ACM Trans. Design Autom. Electr. Syst. 7(3): 474-498 (2002)

34 EE David Blaauw, Luciano Lavagno: Guest Editors' Introduction: Hot Topics at This Year's Design Automation Conference. IEEE Design & Test of Computers 19(4): 72-73 (2002)

33 EE Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David Blaauw: Duet: an accurate leakage estimation and optimization tool for dual-V_t circuits. IEEE Trans. VLSI Syst. 10(2): 79-90 (2002)

32 EE Kaushik Gala, David Blaauw, Vladimir Zolotov, P. M. Vaidya, A. Joshi: Inductance model and analysis methodology for high-speed on-chip interconnect. IEEE Trans. VLSI Syst. 10(6): 730-745 (2002)

31 EE David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran: Slope propagation in static timing analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1180-1195 (2002)

30 EE Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw: Hierarchical analysis of power distribution networks. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 159-168 (2002)

29 EE David Blaauw, Steve Martin, Trevor N. Mudge, Krisztián Flautner: Leakage Current Reduction in VLSI Systems. Journal of Circuits, Systems, and Computers 11(6): 621-636 (2002)

2001

28 EE Kaushik Gala, David Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao: Inductance 101: Analysis and Design Issues. DAC 2001: 329-334

27 EE Supamas Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo: Driver Modeling and Alignment for Worst-Case Delay Noise. DAC 2001: 720-725

26 EE Alexey Glebov, Sergey Gavrilov, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov: False-Noise Analysis using Logic Implications. ICCAD 2001: 515-

25 EE Rajendran Panda, Savithri Sundareswaran, David Blaauw: On the interaction of power distribution network with substrate. ISLPED 2001: 388-393

24 EE David Blaauw, Rajendran Panda: On-Chip Inductance Extraction and Modelin. ISQED 2001: 14

23 EE Murat R. Becer, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj: A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. ISQED 2001: 158-

2000

22 David Blaauw, Christian C. Enz, Thaddeus Gabara, Enrico Macii: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000 ACM 2000

21 EE David Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang: On-chip inductance modeling. ACM Great Lakes Symposium on VLSI 2000: 75-80

20 EE Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David Blaauw: Hierarchical analysis of power distribution networks. DAC 2000: 150-155

19 EE Rajat Chaudhry, David Blaauw, Rajendran Panda, Tim Edwards: Current signature compression for IR-drop analysis. DAC 2000: 162-167

18 EE Rafi Levy, David Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov: ClariNet: a noise analysis tool for deep submicron design. DAC 2000: 233-238

17 EE David Blaauw, Rajendran Panda, Abhijit Das: Removing user specified false paths from timing graphs. DAC 2000: 270-273

16 EE Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David Blaauw: On-chip inductance modeling and analysis. DAC 2000: 63-68

15 David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda: Slope Propagation in Static Timing Analysis. ICCAD 2000: 338-343

14 EE Rajendran Panda, David Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju: Model and analysis for combined package and on-chip power grid simulation. ISLPED 2000: 179-184

13 EE Rajat Chaudhry, Rajendran Panda, Tim Edwards, David Blaauw: Design and Analysis of Power Distribution Networks with Accurate RLC Models. VLSI Design 2000: 151-155

1999

12 Farid N. Najm, Jason Cong, David Blaauw: Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999 ACM 1999

11 EE Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David Blaauw: Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. DAC 1999: 436-441

10 EE Savithri Sundareswaran, David Blaauw, Abhijit Dharchoudhury: A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. VLSI Design 1999: 175-180

1998

9 EE Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David Blaauw: Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. DAC 1998: 388-391

8 EE Abhijit Dharchoudhury, Rajendran Panda, David Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden: Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. DAC 1998: 738-743

7 EE David Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards: Emerging power management tools for processor design. ISLPED 1998: 143-148

1997

6 EE Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, G. Vijayan, David Blaauw: Library-less synthesis for static CMOS combinational logic circuits. ICCAD 1997: 658-662

5 Abhijit Dharchoudhury, David Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning: Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. ICCD 1997: 143-148

1995

4 EE Alexey Glebov, David Blaauw, Larry G. Jones: Transistor reordering for low power CMOS gates using an SP-BDD representation. ISLPD 1995: 161-166

1994

3 EE Larry G. Jones, David Blaauw: A cache-based method for accelerating switch-level simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 211-218 (1994)

1990

2 David Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham: SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. ICCAD 1990: 66-69

1989

1 EE David Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh: Automatic Generation of Behavioral Models from Switch-Level Descriptions. DAC 1989: 179-184

2008
181	EE	Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Stress aware layout optimization. ISPD 2008: 168-174
180	EE	Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw: A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 272-285 (2008)
179	EE	Sarvesh H. Kulkarni, D. M. Sylvester, David T. Blaauw: Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 481-494 (2008)
178	EE	David Blaauw, Kaviraj Chopra, Ashish Srivastava, Louis Scheffer: Statistical Timing Analysis: From Basic Principles to State of the Art. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 589-607 (2008)
2007
177	EE	Sanjay Pant, David Blaauw: Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks. ASP-DAC 2007: 757-762
176	EE	Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer: Top-k Aggressors Sets in Delay Noise Analysis. DAC 2007: 174-179
175	EE	Mingoo Seok, Scott Hanson, Dennis Sylvester, David Blaauw: Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design. DAC 2007: 694-699
174	EE	Scott Hanson, Mingoo Seok, Dennis Sylvester, David Blaauw: Nanometer Device Scaling in Subthreshold Circuits. DAC 2007: 700-705
173	EE	Gregory K. Chen, David Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim: Yield-driven near-threshold SRAM design. ICCAD 2007: 660-666
172	EE	Vivek Joshi, David Blaauw, Dennis Sylvester: Soft-edge flip-flops for improved timing yield: design and optimization. ICCAD 2007: 667-673
171	EE	Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada: Victim alignment in crosstalk aware timing analysis. ICCAD 2007: 698-704
170	EE	Bo Zhai, Ronald G. Dreslinski, David Blaauw, Trevor N. Mudge, Dennis Sylvester: Energy efficient near-threshold chip multi-processing. ISLPED 2007: 32-37
169	EE	Jae-sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, Ram Krishnamurthy: A robust edge encoding technique for energy-efficient multi-cycle interconnect. ISLPED 2007: 68-73
168	EE	Jae-sun Seo, Prashant Singh, Dennis Sylvester, David Blaauw: Self-Time Regenerators for High-Speed and Low-Power Interconnect. ISQED 2007: 621-626
167	EE	Mini Nanua, David Blaauw: Investigating Crosstalk in Sub-Threshold Circuits. ISQED 2007: 639-646
166	EE	Mini Nanua, David Blaauw: Crosstalk Waveform Modeling Using Wave Fitting. PATMOS 2007: 211-221
165	EE	Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction CoRR abs/0710.4679: (2007)
164	EE	Aseem Agarwal, Kaviraj Chopra, David Blaauw: Statistical Timing Based Optimization using Gate Sizing CoRR abs/0710.4697: (2007)
163	EE	Sanjay Pant, Eli Chiprout, David Blaauw: Power Grid Physics and Implications for CAD. IEEE Design & Test of Computers 24(3): 246-254 (2007)
162	EE	Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester: Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 468-479 (2007)
2006
161	EE	Eric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Reliability modeling and management in dynamic microprocessor-based systems. DAC 2006: 1057-1060
160	EE	Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester: An efficient static algorithm for computing the soft error rates of combinational circuits. DATE 2006: 164-169
159	EE	Kaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylvester: A new statistical max operation for propagating skewness in statistical timing analysis. ICCAD 2006: 237-243
158	EE	Sarvesh H. Kulkarni, Dennis Sylvester, David Blaauw: A statistical framework for post-silicon tuning through body bias clustering. ICCAD 2006: 39-46
157	EE	Rajeev R. Rao, David Blaauw, Dennis Sylvester: Soft error reduction in combinational logic using gate resizing and flipflop selection. ICCAD 2006: 502-509
156	EE	Brian Cline, Kaviraj Chopra, David Blaauw, Yu Cao: Analysis and modeling of CD variation for statistical static timing. ICCAD 2006: 60-66
155	EE	Sanjay Pant, David Blaauw: An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks. ICCD 2006
154	EE	David Blaauw, Bo Zhai: Energy efficient design for subthreshold supply voltage operation. ISCAS 2006
153	EE	Scott Hanson, Dennis Sylvester, David Blaauw: A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits. ISLPED 2006: 338-341
152	EE	Scott Hanson, Bo Zhai, David Blaauw, Dennis Sylvester, Andres Bryant, Xinlin Wang: Energy optimality and variability in subthreshold design. ISLPED 2006: 363-365
151	EE	Vivek Joshi, Rajeev R. Rao, David Blaauw, Dennis Sylvester: Logic SER Reduction through Flipflop Redesign. ISQED 2006: 611-616
150	EE	Mini Nanua, David Blaauw: Receiver Modeling for Static Functional Crosstalk Analysis. PATMOS 2006: 329-339
149	EE	Scott Hanson, Bo Zhai, Kerry Bernstein, David Blaauw, Andres Bryant, Leland Chang, Koushik K. Das, Wilfried Haensch, Edward J. Nowak, Dennis Sylvester: Ultralow-voltage, minimum-energy CMOS. IBM Journal of Research and Development 50(4-5): 469-490 (2006)
148	EE	Dongwoo Lee, David Blaauw, Dennis Sylvester: Runtime Leakage Minimization Through Probability-Aware Optimization. IEEE Trans. VLSI Syst. 14(10): 1075-1088 (2006)
147	EE	Kanak Agarwal, Dennis Sylvester, David Blaauw: Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 892-901 (2006)
146	EE	Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David Blaauw: Statistical interconnect metrics for physical-design optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1273-1288 (2006)
145	EE	Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Analytical yield prediction considering leakage/performance correlation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1685-1695 (2006)
2005
144	EE	Amit Jain, David Blaauw: Slack borrowing in flip-flop based sequential circuits. ACM Great Lakes Symposium on VLSI 2005: 96-101
143	EE	Kanak Agarwal, Dennis Sylvester, David Blaauw, Anirudh Devgan: Achieving continuous V_T performance in a dual V_T process. ASP-DAC 2005: 393-398
142	EE	David Blaauw, Anirudh Devgan, Farid N. Najm: Leakage power: trends, analysis and avoidance. ASP-DAC 2005
141	EE	Todd M. Austin, Valeria Bertacco, David Blaauw, Trevor N. Mudge: Opportunities and challenges for better than worst-case design. ASP-DAC 2005: 2-7
140	EE	Dongwoo Lee, David Blaauw, Dennis Sylvester: Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment. ASP-DAC 2005: 399-404
139	EE	Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David Blaauw: Statistical modeling of cross-coupling effects in VLSI interconnects. ASP-DAC 2005: 503-506
138	EE	Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David Blaauw: A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution. CASES 2005: 249-256
137	EE	Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladimir Zolotov: Circuit optimization using statistical static timing analysis. DAC 2005: 321-324
136	EE	Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director: Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. DAC 2005: 535-540
135	EE	David Blaauw, Kaviraj Chopra: CAD tools for variation tolerance. DAC 2005: 766
134	EE	Aseem Agarwal, Kaviraj Chopra, David Blaauw: Statistical Timing Based Optimization using Gate Sizing. DATE 2005: 400-405
133	EE	Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction. DATE 2005: 80-85
132		Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David Blaauw, Dennis Sylvester: Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. ICCAD 2005: 1023-1028
131		Sanjay Pant, David Blaauw: Static timing analysis considering power supply variations. ICCAD 2005: 365-371
130		Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David Blaauw, Vladimir Zolotov: Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. ICCAD 2005: 705-712
129		Amit Jain, David Blaauw, Vladimir Zolotov: Accurate delay computation for noisy waveform shapes. ICCAD 2005: 947-953
128	EE	Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd M. Austin, David Blaauw: Energy Optimization of Subthreshold-Voltage Sensor Network Processors. ISCA 2005: 197-207
127	EE	Eric Karl, Dennis Sylvester, David Blaauw: Timing error correction techniques for voltage-scalable on-chip memories. ISCAS (4) 2005: 3563-3566
126	EE	Bo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester: Analysis and mitigation of variability in subthreshold design. ISLPED 2005: 20-25
125	EE	Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif: An efficient surface-based low-power buffer insertion algorithm. ISPD 2005: 86-93
124	EE	Mini Nanua, David Blaauw, Chanhee Oh: Leakage Current Modeling in PD SOI Circuits. ISQED 2005: 113-117
123	EE	Harmander Deogun, Dennis Sylvester, David Blaauw: Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate. ISQED 2005: 175-180
122	EE	David Roberts, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner: Error Analysis for the Support of Robust Voltage Scaling. ISQED 2005: 65-70
121	EE	Rajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan: Modeling and Analysis of Parametric Yield under Power and Performance Constraints. IEEE Design & Test of Computers 22(4): 376-385 (2005)
120	EE	Nam Sung Kim, David Blaauw, Trevor N. Mudge: Quantitative analysis and optimization techniques for on-chip cache leakage power. IEEE Trans. VLSI Syst. 13(10): 1147-1156 (2005)
119	EE	Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner: The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. IEEE Trans. VLSI Syst. 13(11): 1239-1252 (2005)
118	EE	Rajeev R. Rao, Harmander Deogun, David Blaauw, Dennis Sylvester: Bus encoding for total power reduction using a leakage-aware buffer configuration. IEEE Trans. VLSI Syst. 13(12): 1376-1383 (2005)
117	EE	Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: Probability distribution of signal arrival times using Bayesian networks. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1784-1794 (2005)
116	EE	Dongwoo Lee, David Blaauw, Dennis Sylvester: Static leakage reduction through simultaneous V/sub t//T/sub ox/ and state assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1014-1029 (2005)
2004
115	EE	Kanak Agarwal, Dennis Sylvester, David Blaauw: A simplified transmission-line based crosstalk noise model for on-chip RLC wiring. ASP-DAC 2004: 858-864
114	EE	Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: A stochastic approach To power grid analysis. DAC 2004: 171-176
113	EE	Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge: Circuit-aware architectural simulation. DAC 2004: 305-310
112	EE	Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula: Variational delay metrics for interconnect timing analysis. DAC 2004: 381-384
111	EE	Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Parametric yield estimation considering leakage variability. DAC 2004: 442-447
110	EE	Aseem Agarwal, Florentin Dartu, David Blaauw: Statistical gate delay model considering multiple input switching. DAC 2004: 658-663
109	EE	Dongwoo Lee, Vladimir Zolotov, David Blaauw: Static timing analysis using backward signal propagation. DAC 2004: 664-669
108	EE	Ashish Srivastava, Dennis Sylvester, David Blaauw: Statistical optimization of leakage power considering process variations using dual-Vth and sizing. DAC 2004: 773-778
107	EE	Harmander Deogun, Rajeev R. Rao, Dennis Sylvester, David Blaauw: Leakage-and crosstalk-aware bus encoding for total power reduction. DAC 2004: 779-782
106	EE	Ashish Srivastava, Dennis Sylvester, David Blaauw: Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. DAC 2004: 783-787
105	EE	Bo Zhai, David Blaauw, Dennis Sylvester, Krisztián Flautner: Theoretical and practical limits of dynamic voltage scaling. DAC 2004: 868-873
104	EE	Dongwoo Lee, Harmander Deogun, David Blaauw, Dennis Sylvester: Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization. DATE 2004: 494-499
103	EE	Ashish Srivastava, Dennis Sylvester, David Blaauw: Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design. DATE 2004: 718-719
102	EE	Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David Blaauw, Trevor N. Mudge: Reducing pipeline energy demands with local DVS and dynamic retiming. ISLPED 2004: 319-324
101	EE	Woo Hyung Lee, Sanjay Pant, David Blaauw: Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids. ISQED 2004: 131-136
100	EE	Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner: Making Typical Silicon Matter with Razor. IEEE Computer 37(3): 57-65 (2004)
99	EE	Todd M. Austin, David Blaauw, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Wayne Wolf: Mobile Supercomputers. IEEE Computer 37(5): 81-83 (2004)
98	EE	Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner: Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. IEEE Micro 24(6): 10-20 (2004)
97		Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical analysis of subthreshold leakage current for VLSI circuits. IEEE Trans. VLSI Syst. 12(2): 131-139 (2004)
96		Dongwoo Lee, David Blaauw, Dennis Sylvester: Gate oxide leakage current analysis and reduction for VLSI circuits. IEEE Trans. VLSI Syst. 12(2): 155-166 (2004)
95		Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge: Circuit and microarchitectural techniques for reducing cache leakage power. IEEE Trans. VLSI Syst. 12(2): 167-184 (2004)
94	EE	Kanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driver output model for on-chip RLC transmission lines. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 128-136 (2004)
93	EE	Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Postroute gate sizing for crosstalk noise reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1670-1677 (2004)
92	EE	Aseem Agarwal, Vladimir Zolotov, David Blaauw: Statistical clock skew analysis considering intradie-process variations. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1231-1242 (2004)
91	EE	Kanak Agarwal, Dennis Sylvester, David Blaauw: A simple metric for slew rate of RC circuits based on two circuit moments. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1346-1354 (2004)
2003
90	EE	Jan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang: Reshaping EDA for power. DAC 2003: 15
89	EE	Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester: Analysis and minimization techniques for total leakage considering gate oxide leakage. DAC 2003: 175-180
88	EE	Dongwoo Lee, David Blaauw: Static leakage reduction through simultaneous threshold voltage and state assignment. DAC 2003: 191-194
87	EE	Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Computation and Refinement of Statistical Bounds on Circuit Delay. DAC 2003: 348-353
86	EE	Kanak Agarwal, Dennis Sylvester, David Blaauw: An effective capacitance based driver output model for on-chip RLC interconnects. DAC 2003: 376-381
85	EE	Bhavana Thudi, David Blaauw: Non-iterative switching window computation for delay-noise. DAC 2003: 390-395
84	EE	Kanak Agarwal, Dennis Sylvester, David Blaauw: Simple metrics for slew rate of RC circuits based on two circuit moments. DAC 2003: 950-953
83	EE	Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Post-route gate sizing for crosstalk noise reduction. DAC 2003: 954-957
82	EE	Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical Timing Analysis Using Bounds. DATE 2003: 10062-10067
81	EE	D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David Blaauw, Rajendran Panda, Murat R. Becer, A. Ardelea, A. Patel: SOI Transistor Model for Fast Transient Simulation. ICCAD 2003: 120128
80	EE	Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: Vectorless Analysis of Supply Noise Induced Delay Variation. ICCAD 2003: 184-192
79	EE	Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: AU: Timing Analysis Under Uncertainty. ICCAD 2003: 615-620
78	EE	Nam Sung Kim, David Blaauw, Trevor N. Mudge: Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches. ICCAD 2003: 627-632
77	EE	Aseem Agarwal, David Blaauw, Vladimir Zolotov: Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations. ICCAD 2003: 900-907
76	EE	Aseem Agarwal, David Blaauw, Vladimir Zolotov: Statistical Clock Skew Analysis Considering Intra-Die Process Variations. ICCAD 2003: 914-921
75	EE	Shidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester: Optimal Inductance for On-chip RLC Interconnections. ICCD 2003: 264-
74	EE	Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) 2003: 668-671
73	EE	Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical estimation of leakage current considering inter- and intra-die process variation. ISLPED 2003: 84-89
72	EE	Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Post-Route Gate Sizing for Crosstalk Noise Reduction. ISQED 2003: 171-176
71	EE	Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester: Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design. ISQED 2003: 287-292
70	EE	Chanhee Oh, David Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta: Static Electromigration Analysis for Signal Interconnects. ISQED 2003: 377-
69	EE	Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David Blaauw: An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages. ISVLSI 2003: 149-154
68	EE	Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge: Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. MICRO 2003: 7-18
67	EE	Nam Sung Kim, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan: Leakage Current: Moore's Law Meets Static Power. IEEE Computer 36(12): 68-75 (2003)
66	EE	Rajendran Panda, Savithri Sundareswaran, David Blaauw: Impact of Low-Impedance Substrate on Power Supply Integrity. IEEE Design & Test of Computers 20(3): 16-22 (2003)
65	EE	David Blaauw, Supamas Sirichotiyakul, Chanhee Oh: Driver modeling and alignment for worst-case delay noise. IEEE Trans. VLSI Syst. 11(2): 157-166 (2003)
64	EE	David Blaauw, Chanhee Oh, Vladimir Zolotov, Aurobindo Dasgupta: Static electromigration analysis for on-chip signal interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 39-48 (2003)
63	EE	Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 49-66 (2003)
62	EE	Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj: Early probabilistic noise estimation for capacitively coupled interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 337-345 (2003)
61	EE	Li Ding, David T. Blaauw, Pinaki Mazumder: Accurate crosstalk noise modeling for early signal integrity analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 627-634 (2003)
60	EE	David T. Blaauw, Luciano Lavagno: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 962-963 (2003)
59	EE	Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul: Probabilistic analysis of interconnect coupling noise. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1188-1203 (2003)
58	EE	Aseem Agarwal, Vladimir Zolotov, David T. Blaauw: Statistical timing analysis using bounds and selective enumeration. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1243-1260 (2003)
2002
57	EE	Himanshu Kaul, Dennis Sylvester, David Blaauw: Active shields: a new approach to shielding global wires. ACM Great Lakes Symposium on VLSI 2002: 112-117
56	EE	Sarma B. K. Vrudhula, David Blaauw, Supamas Sirichotiyakul: Estimation of the likelihood of capacitive coupling noise. DAC 2002: 653-658
55	EE	Murat R. Becer, Vladimir Zolotov, David Blaauw, Rajendran Panda, Ibrahim N. Hajj: Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . DATE 2002: 456-464
54	EE	Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: A precorrected-FFT method for simulating on-chip inductance. ICCAD 2002: 221-227
53	EE	Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: Estimation of signal arrival times in the presence of delay noise. ICCAD 2002: 418-422
52	EE	Vladimir Zolotov, David Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy: Noise propagation and failure criteria for VLSI designs. ICCAD 2002: 587-594
51	EE	Li Ding, David Blaauw, Pinaki Mazumder: Efficient crosstalk noise modeling using aggressor and tree reductions. ICCAD 2002: 595-600
50	EE	Steven M. Martin, Krisztián Flautner, Trevor N. Mudge, David Blaauw: Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. ICCAD 2002: 721-725
49	EE	Krisztián Flautner, Nam Sung Kim, Steve Martin, David Blaauw, Trevor N. Mudge: Drowsy Caches: Simple Techniques for Reducing Leakage Power. ISCA 2002: 148-157
48	EE	Li Ding, Pinaki Mazumder, David Blaauw: Crosstalk noise estimation using effective coupling capacitance. ISCAS (5) 2002: 645-648
47	EE	Ashish Srivastava, Robert Bai, David Blaauw, Dennis Sylvester: Modeling and analysis of leakage power considering within-die process variations. ISLPED 2002: 64-67
46	EE	Murat R. Becer, Rajendran Panda, David Blaauw, Ibrahim N. Hajj: Pre-route Noise Estimation in Deep Submicron Integrated Circuits. ISQED 2002: 413-418
45	EE	Vladimir Zolotov, David Blaauw, Rajendran Panda, Chanhee Oh: Noise Injection and Propagation in High Performance Designs. ISQED 2002: 425-430
44	EE	Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh: False-Noise Analysis Using Resolution Method. ISQED 2002: 437-
43	EE	Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge: Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. MICRO 2002: 219-230
42	EE	Fadi A. Aloul, Soha Hassoun, Karem A. Sakallah, David Blaauw: Robust SAT-Based Search Algorithm for Leakage Power Reduction. PATMOS 2002: 167-177
41	EE	Murat R. Becer, David Blaauw, Ibrahim N. Hajj, Rajendran Panda: Early probabilistic noise estimation for capacitively coupled interconnects. SLIP 2002: 77-83
40	EE	Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 16-21
39	EE	Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 29-36
38	EE	Kanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driving point model for on-chip RLC interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 63-69
37	EE	Bhavana Thudi, David Blaauw: Efficient switching window computation for cross-talk noise. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 84-91
36	EE	Himanshu Kaul, Dennis Sylvester, David Blaauw: Active shielding of RLC global interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 98-104
35	EE	Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov: False-noise analysis using logic implications. ACM Trans. Design Autom. Electr. Syst. 7(3): 474-498 (2002)
34	EE	David Blaauw, Luciano Lavagno: Guest Editors' Introduction: Hot Topics at This Year's Design Automation Conference. IEEE Design & Test of Computers 19(4): 72-73 (2002)
33	EE	Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David Blaauw: Duet: an accurate leakage estimation and optimization tool for dual-V_t circuits. IEEE Trans. VLSI Syst. 10(2): 79-90 (2002)
32	EE	Kaushik Gala, David Blaauw, Vladimir Zolotov, P. M. Vaidya, A. Joshi: Inductance model and analysis methodology for high-speed on-chip interconnect. IEEE Trans. VLSI Syst. 10(6): 730-745 (2002)
31	EE	David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran: Slope propagation in static timing analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1180-1195 (2002)
30	EE	Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw: Hierarchical analysis of power distribution networks. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 159-168 (2002)
29	EE	David Blaauw, Steve Martin, Trevor N. Mudge, Krisztián Flautner: Leakage Current Reduction in VLSI Systems. Journal of Circuits, Systems, and Computers 11(6): 621-636 (2002)
2001
28	EE	Kaushik Gala, David Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao: Inductance 101: Analysis and Design Issues. DAC 2001: 329-334
27	EE	Supamas Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo: Driver Modeling and Alignment for Worst-Case Delay Noise. DAC 2001: 720-725
26	EE	Alexey Glebov, Sergey Gavrilov, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov: False-Noise Analysis using Logic Implications. ICCAD 2001: 515-
25	EE	Rajendran Panda, Savithri Sundareswaran, David Blaauw: On the interaction of power distribution network with substrate. ISLPED 2001: 388-393
24	EE	David Blaauw, Rajendran Panda: On-Chip Inductance Extraction and Modelin. ISQED 2001: 14
23	EE	Murat R. Becer, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj: A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. ISQED 2001: 158-
2000
22		David Blaauw, Christian C. Enz, Thaddeus Gabara, Enrico Macii: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000 ACM 2000
21	EE	David Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang: On-chip inductance modeling. ACM Great Lakes Symposium on VLSI 2000: 75-80
20	EE	Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David Blaauw: Hierarchical analysis of power distribution networks. DAC 2000: 150-155
19	EE	Rajat Chaudhry, David Blaauw, Rajendran Panda, Tim Edwards: Current signature compression for IR-drop analysis. DAC 2000: 162-167
18	EE	Rafi Levy, David Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov: ClariNet: a noise analysis tool for deep submicron design. DAC 2000: 233-238
17	EE	David Blaauw, Rajendran Panda, Abhijit Das: Removing user specified false paths from timing graphs. DAC 2000: 270-273
16	EE	Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David Blaauw: On-chip inductance modeling and analysis. DAC 2000: 63-68
15		David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda: Slope Propagation in Static Timing Analysis. ICCAD 2000: 338-343
14	EE	Rajendran Panda, David Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju: Model and analysis for combined package and on-chip power grid simulation. ISLPED 2000: 179-184
13	EE	Rajat Chaudhry, Rajendran Panda, Tim Edwards, David Blaauw: Design and Analysis of Power Distribution Networks with Accurate RLC Models. VLSI Design 2000: 151-155
1999
12		Farid N. Najm, Jason Cong, David Blaauw: Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999 ACM 1999
11	EE	Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David Blaauw: Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. DAC 1999: 436-441
10	EE	Savithri Sundareswaran, David Blaauw, Abhijit Dharchoudhury: A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. VLSI Design 1999: 175-180
1998
9	EE	Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David Blaauw: Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. DAC 1998: 388-391
8	EE	Abhijit Dharchoudhury, Rajendran Panda, David Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden: Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. DAC 1998: 738-743
7	EE	David Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards: Emerging power management tools for processor design. ISLPED 1998: 143-148
1997
6	EE	Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, G. Vijayan, David Blaauw: Library-less synthesis for static CMOS combinational logic circuits. ICCAD 1997: 658-662
5		Abhijit Dharchoudhury, David Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning: Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. ICCD 1997: 143-148
1995
4	EE	Alexey Glebov, David Blaauw, Larry G. Jones: Transistor reordering for low power CMOS gates using an SP-BDD representation. ISLPD 1995: 161-166
1994
3	EE	Larry G. Jones, David Blaauw: A cache-based method for accelerating switch-level simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 211-218 (1994)
1990
2		David Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham: SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. ICCAD 1990: 66-69
1989
1	EE	David Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh: Automatic Generation of Behavioral Models from Switch-Level Descriptions. DAC 1989: 179-184

Coauthor Index

1 Jacob A. Abraham [1] [2]

2 Aseem Agarwal [39] [40] [58] [76] [77] [82] [87] [92] [110] [134] [137] [164]

3 Kanak Agarwal [38] [75] [84] [86] [91] [94] [112] [115] [136] [139] [143] [146] [147] [181]

4 Mridul Agarwal [139] [146]

5 Ilan Algor [72] [83] [93]

6 Fadi A. Aloul [42]

7 Charles J. Alpert [125]

8 A. Ardelea [81]

9 Todd M. Austin [67] [68] [98] [99] [100] [102] [113] [122] [128] [133] [138] [141] [165]

10 Robert Bai [47] [69]

11 Prithviraj Banerjee (Prith Banerjee) [2]

12 David Bearden [8]

13 Murat R. Becer [23] [41] [46] [52] [55] [62] [70] [72] [81] [83] [93] [171] [176]

14 Kerry Bernstein [90] [149]

15 Valeria Bertacco [113] [141]

16 Sarvesh Bhardwaj [53] [79] [117]

17 Gabi Braca [18]

18 Andres Bryant [149] [152]

19 Yu Cao [156]

20 Chaitali Chakrabarti [99]

21 Leland Chang [149]

22 Rajat Chaudhry [13] [14] [19] [20]

23 Gregory K. Chen [173]

24 Eli Chiprout [163]

25 Kaviraj Chopra [132] [134] [135] [137] [156] [159] [160] [162] [164] [171] [176] [178] [180]

26 Brian Cline [156] [181]

27 Jason Cong [12]

28 Florentin Dartu [110]

29 Abhijit Das [17]

30 Koushik K. Das [149]

31 Shidhartha Das [68] [75] [98] [102] [113]

32 Aurobindo Dasgupta [18] [64] [70]

33 Harmander Deogun [104] [107] [118] [123]

34 Anirudh Devgan [111] [121] [142] [143] [145]

35 Abhijit Dharchoudhury [5] [6] [7] [8] [9] [10] [11]

36 Li Ding [48] [51] [61]

37 Stephen W. Director [136]

38 Ronald G. Dreslinski [170]

39 J. Dunning [5]

40 Tim Edwards [7] [9] [11] [13] [19] [20] [33]

41 Y. Egorov [81]

42 Christian C. Enz [22]

43 Dan Ernst [68] [98]

44 Krisztián Flautner [29] [43] [49] [50] [67] [68] [95] [98] [100] [105] [119] [122]

45

1	Jacob A. Abraham	[1] [2]
2	Aseem Agarwal	[39] [40] [58] [76] [77] [82] [87] [92] [110] [134] [137] [164]
3	Kanak Agarwal	[38] [75] [84] [86] [91] [94] [112] [115] [136] [139] [143] [146] [147] [181]
4	Mridul Agarwal	[139] [146]
5	Ilan Algor	[72] [83] [93]
6	Fadi A. Aloul	[42]
7	Charles J. Alpert	[125]
8	A. Ardelea	[81]
9	Todd M. Austin	[67] [68] [98] [99] [100] [102] [113] [122] [128] [133] [138] [141] [165]
10	Robert Bai	[47] [69]
11	Prithviraj Banerjee (Prith Banerjee)	[2]
12	David Bearden	[8]
13	Murat R. Becer	[23] [41] [46] [52] [55] [62] [70] [72] [81] [83] [93] [171] [176]
14	Kerry Bernstein	[90] [149]
15	Valeria Bertacco	[113] [141]
16	Sarvesh Bhardwaj	[53] [79] [117]
17	Gabi Braca	[18]
18	Andres Bryant	[149] [152]
19	Yu Cao	[156]
20	Chaitali Chakrabarti	[99]
21	Leland Chang	[149]
22	Rajat Chaudhry	[13] [14] [19] [20]
23	Gregory K. Chen	[173]
24	Eli Chiprout	[163]
25	Kaviraj Chopra	[132] [134] [135] [137] [156] [159] [160] [162] [164] [171] [176] [178] [180]
26	Brian Cline	[156] [181]
27	Jason Cong	[12]
28	Florentin Dartu	[110]
29	Abhijit Das	[17]
30	Koushik K. Das	[149]
31	Shidhartha Das	[68] [75] [98] [102] [113]
32	Aurobindo Dasgupta	[18] [64] [70]
33	Harmander Deogun	[104] [107] [118] [123]
34	Anirudh Devgan	[111] [121] [142] [143] [145]
35	Abhijit Dharchoudhury	[5] [6] [7] [8] [9] [10] [11]
36	Li Ding	[48] [51] [61]
37	Stephen W. Director	[136]
38	Ronald G. Dreslinski	[170]
39	J. Dunning	[5]
40	Tim Edwards	[7] [9] [11] [13] [19] [20] [33]
41	Y. Egorov	[81]
42	Christian C. Enz	[22]
43	Dan Ernst	[68] [98]
44	Krisztián Flautner	[29] [43] [49] [50] [67] [68] [95] [98] [100] [105] [119] [122]
45