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David Blaauw Vis

David T. Blaauw

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*2009
207EEShidhartha Das, David Blaauw, David Bull, Krisztián Flautner, Rob Aitken: Addressing design margins through error-tolerant circuits. DAC 2009: 11-12
206EERavikishore Gandikota, Li Ding, Peivand Tehrani, David Blaauw: Worst-case aggressor-victim alignment with current-source driver models. DAC 2009: 13-18
205EEVineeth Veetil, Dennis Sylvester, David Blaauw, Saumil Shah, Steffen Rochel: Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence. DAC 2009: 154-159
204EEDavid Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David Blaauw, Dennis Sylvester: Vicis: a reliable network for unreliable silicon. DAC 2009: 812-817
203EEDavid Fick, Andrew DeOrio, Gregory K. Chen, Valeria Bertacco, Dennis Sylvester, David Blaauw: A highly resilient routing algorithm for fault-tolerant NoCs. DATE 2009: 21-26
202EERonald G. Dreslinski, David Fick, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Reconfigurable Multicore Server Processors for Low Power Operation. SAMOS 2009: 247-254
2008
201EEVineeth Veetil, Dennis Sylvester, David Blaauw: Efficient Monte Carlo based incremental statistical timing analysis. DAC 2008: 676-681
200EEVivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Leakage power reduction using stress-enhanced layouts. DAC 2008: 912-917
199EERavikishore Gandikota, David Blaauw, Dennis Sylvester: Modeling crosstalk in statistical static timing analysis. DAC 2008: 974-979
198EEBrian Cline, Kaviraj Chopra, David Blaauw, Andres Torres, Savithri Sundareswaran: Transistor-Specific Delay Modeling for SSTA. DATE 2008: 592-597
197EEJae-sun Seo, Igor L. Markov, Dennis Sylvester, David Blaauw: On the decreasing significance of large standard cells in technology mapping. ICCAD 2008: 116-121
196EEBrian Cline, Vivek Joshi, Dennis Sylvester, David Blaauw: STEEL: a technique for stress-enhanced standard cell library design. ICCAD 2008: 691-697
195EEKaviraj Chopra, Cheng Zhuo, David Blaauw, Dennis Sylvester: A statistical approach for full-chip gate-oxide reliability analysis. ICCAD 2008: 698-705
194EEYu-Shiang Lin, Scott Hanson, Fabio Albano, Carlos Tokunaga, Razi-Ul Haque, Kensall Wise, Ann Marie Sastry, David Blaauw, Dennis Sylvester: Low-voltage circuit design for widespread sensing applications. ISCAS 2008: 2558-2561
193EECheng Zhuo, David Blaauw, Dennis Sylvester: Variation-aware gate sizing and clustering for post-silicon optimized circuits. ISLPED 2008: 105-110
192EEMingoo Seok, Dennis Sylvester, David Blaauw: Optimal technology selection for minimizing energy and variability in low voltage applications. ISLPED 2008: 9-14
191EEVivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Stress aware layout optimization. ISPD 2008: 168-174
190EEEric Karl, Dennis Sylvester, David Blaauw: Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures. ISQED 2008: 391-395
189EEVineeth Veetil, Dennis Sylvester, David Blaauw: Fast and Accurate Waveform Analysis with Current Source Models. ISQED 2008: 53-56
188EERonald G. Dreslinski, Gregory K. Chen, Trevor N. Mudge, David Blaauw, Dennis Sylvester, Krisztián Flautner: Reconfigurable energy efficient near threshold cache architectures. MICRO 2008: 459-470
187EEEric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Multi-Mechanism Reliability Modeling and Management in Dynamic Systems. IEEE Trans. VLSI Syst. 16(4): 476-487 (2008)
186EEPrashant Singh, Jae-sun Seo, David Blaauw, Dennis Sylvester: Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect. IEEE Trans. VLSI Syst. 16(6): 673-677 (2008)
185EEAshish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw: A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 272-285 (2008)
184EESarvesh H. Kulkarni, D. M. Sylvester, David T. Blaauw: Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 481-494 (2008)
183EEDavid Blaauw, Kaviraj Chopra, Ashish Srivastava, Louis Scheffer: Statistical Timing Analysis: From Basic Principles to State of the Art. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 589-607 (2008)
2007
182EESanjay Pant, David Blaauw: Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks. ASP-DAC 2007: 757-762
181EERavikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer: Top-k Aggressors Sets in Delay Noise Analysis. DAC 2007: 174-179
180EEMingoo Seok, Scott Hanson, Dennis Sylvester, David Blaauw: Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design. DAC 2007: 694-699
179EEScott Hanson, Mingoo Seok, Dennis Sylvester, David Blaauw: Nanometer Device Scaling in Subthreshold Circuits. DAC 2007: 700-705
178EEGregory K. Chen, David Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim: Yield-driven near-threshold SRAM design. ICCAD 2007: 660-666
177EEVivek Joshi, David Blaauw, Dennis Sylvester: Soft-edge flip-flops for improved timing yield: design and optimization. ICCAD 2007: 667-673
176EERavikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada: Victim alignment in crosstalk aware timing analysis. ICCAD 2007: 698-704
175EEBo Zhai, Ronald G. Dreslinski, David Blaauw, Trevor N. Mudge, Dennis Sylvester: Energy efficient near-threshold chip multi-processing. ISLPED 2007: 32-37
174EEJae-sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, Ram Krishnamurthy: A robust edge encoding technique for energy-efficient multi-cycle interconnect. ISLPED 2007: 68-73
173EEJae-sun Seo, Prashant Singh, Dennis Sylvester, David Blaauw: Self-Time Regenerators for High-Speed and Low-Power Interconnect. ISQED 2007: 621-626
172EEMini Nanua, David Blaauw: Investigating Crosstalk in Sub-Threshold Circuits. ISQED 2007: 639-646
171EERonald G. Dreslinski, Bo Zhai, Trevor N. Mudge, David Blaauw, Dennis Sylvester: An Energy Efficient Parallel Architecture Using Near Threshold Operation. PACT 2007: 175-188
170EEMini Nanua, David Blaauw: Crosstalk Waveform Modeling Using Wave Fitting. PATMOS 2007: 211-221
169EEHimanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction CoRR abs/0710.4679: (2007)
168EEAseem Agarwal, Kaviraj Chopra, David Blaauw: Statistical Timing Based Optimization using Gate Sizing CoRR abs/0710.4697: (2007)
167EESanjay Pant, Eli Chiprout, David Blaauw: Power Grid Physics and Implications for CAD. IEEE Design & Test of Computers 24(3): 246-254 (2007)
166EERajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester: Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 468-479 (2007)
2006
165EEEric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Reliability modeling and management in dynamic microprocessor-based systems. DAC 2006: 1057-1060
164EERajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester: An efficient static algorithm for computing the soft error rates of combinational circuits. DATE 2006: 164-169
163EEKaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylvester: A new statistical max operation for propagating skewness in statistical timing analysis. ICCAD 2006: 237-243
162EESarvesh H. Kulkarni, Dennis Sylvester, David Blaauw: A statistical framework for post-silicon tuning through body bias clustering. ICCAD 2006: 39-46
161EERajeev R. Rao, David Blaauw, Dennis Sylvester: Soft error reduction in combinational logic using gate resizing and flipflop selection. ICCAD 2006: 502-509
160EEBrian Cline, Kaviraj Chopra, David Blaauw, Yu Cao: Analysis and modeling of CD variation for statistical static timing. ICCAD 2006: 60-66
159EESanjay Pant, David Blaauw: An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks. ICCD 2006
158EEDavid Blaauw, Bo Zhai: Energy efficient design for subthreshold supply voltage operation. ISCAS 2006
157EEScott Hanson, Dennis Sylvester, David Blaauw: A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits. ISLPED 2006: 338-341
156EEScott Hanson, Bo Zhai, David Blaauw, Dennis Sylvester, Andres Bryant, Xinlin Wang: Energy optimality and variability in subthreshold design. ISLPED 2006: 363-365
155EEVivek Joshi, Rajeev R. Rao, David Blaauw, Dennis Sylvester: Logic SER Reduction through Flipflop Redesign. ISQED 2006: 611-616
154EEMini Nanua, David Blaauw: Receiver Modeling for Static Functional Crosstalk Analysis. PATMOS 2006: 329-339
153EEScott Hanson, Bo Zhai, Kerry Bernstein, David Blaauw, Andres Bryant, Leland Chang, Koushik K. Das, Wilfried Haensch, Edward J. Nowak, Dennis Sylvester: Ultralow-voltage, minimum-energy CMOS. IBM Journal of Research and Development 50(4-5): 469-490 (2006)
152EEDennis Sylvester, David Blaauw, Eric Karl: ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon. IEEE Design & Test of Computers 23(6): 484-490 (2006)
151EEDongwoo Lee, David Blaauw, Dennis Sylvester: Runtime Leakage Minimization Through Probability-Aware Optimization. IEEE Trans. VLSI Syst. 14(10): 1075-1088 (2006)
150EEKanak Agarwal, Dennis Sylvester, David Blaauw: Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 892-901 (2006)
149EEKanak Agarwal, Mridul Agarwal, Dennis Sylvester, David Blaauw: Statistical interconnect metrics for physical-design optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1273-1288 (2006)
148EERajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Analytical yield prediction considering leakage/performance correlation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1685-1695 (2006)
2005
147EEAmit Jain, David Blaauw: Slack borrowing in flip-flop based sequential circuits. ACM Great Lakes Symposium on VLSI 2005: 96-101
146EEKanak Agarwal, Dennis Sylvester, David Blaauw, Anirudh Devgan: Achieving continuous VT performance in a dual VT process. ASP-DAC 2005: 393-398
145EEDavid Blaauw, Anirudh Devgan, Farid N. Najm: Leakage power: trends, analysis and avoidance. ASP-DAC 2005
144EETodd M. Austin, Valeria Bertacco, David Blaauw, Trevor N. Mudge: Opportunities and challenges for better than worst-case design. ASP-DAC 2005: 2-7
143EEDongwoo Lee, David Blaauw, Dennis Sylvester: Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment. ASP-DAC 2005: 399-404
142EEMridul Agarwal, Kanak Agarwal, Dennis Sylvester, David Blaauw: Statistical modeling of cross-coupling effects in VLSI interconnects. ASP-DAC 2005: 503-506
141EELeyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David Blaauw: A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution. CASES 2005: 249-256
140EEAseem Agarwal, Kaviraj Chopra, David Blaauw, Vladimir Zolotov: Circuit optimization using statistical static timing analysis. DAC 2005: 321-324
139EEAshish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director: Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. DAC 2005: 535-540
138EEDavid Blaauw, Kaviraj Chopra: CAD tools for variation tolerance. DAC 2005: 766
137EEAseem Agarwal, Kaviraj Chopra, David Blaauw: Statistical Timing Based Optimization using Gate Sizing. DATE 2005: 400-405
136EEHimanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction. DATE 2005: 80-85
135 Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David Blaauw, Dennis Sylvester: Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. ICCAD 2005: 1023-1028
134 Sanjay Pant, David Blaauw: Static timing analysis considering power supply variations. ICCAD 2005: 365-371
133 Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David Blaauw, Vladimir Zolotov: Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. ICCAD 2005: 705-712
132 Amit Jain, David Blaauw, Vladimir Zolotov: Accurate delay computation for noisy waveform shapes. ICCAD 2005: 947-953
131EELeyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd M. Austin, David Blaauw: Energy Optimization of Subthreshold-Voltage Sensor Network Processors. ISCA 2005: 197-207
130EEEric Karl, Dennis Sylvester, David Blaauw: Timing error correction techniques for voltage-scalable on-chip memories. ISCAS (4) 2005: 3563-3566
129EEBo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester: Analysis and mitigation of variability in subthreshold design. ISLPED 2005: 20-25
128EERajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif: An efficient surface-based low-power buffer insertion algorithm. ISPD 2005: 86-93
127EEMini Nanua, David Blaauw, Chanhee Oh: Leakage Current Modeling in PD SOI Circuits. ISQED 2005: 113-117
126EEHarmander Deogun, Dennis Sylvester, David Blaauw: Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate. ISQED 2005: 175-180
125EEDavid Roberts, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner: Error Analysis for the Support of Robust Voltage Scaling. ISQED 2005: 65-70
124EERajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan: Modeling and Analysis of Parametric Yield under Power and Performance Constraints. IEEE Design & Test of Computers 22(4): 376-385 (2005)
123EENam Sung Kim, David Blaauw, Trevor N. Mudge: Quantitative analysis and optimization techniques for on-chip cache leakage power. IEEE Trans. VLSI Syst. 13(10): 1147-1156 (2005)
122EEBo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner: The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. IEEE Trans. VLSI Syst. 13(11): 1239-1252 (2005)
121EERajeev R. Rao, Harmander Deogun, David Blaauw, Dennis Sylvester: Bus encoding for total power reduction using a leakage-aware buffer configuration. IEEE Trans. VLSI Syst. 13(12): 1376-1383 (2005)
120EESarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: Probability distribution of signal arrival times using Bayesian networks. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1784-1794 (2005)
119EEDongwoo Lee, David Blaauw, Dennis Sylvester: Static leakage reduction through simultaneous V/sub t//T/sub ox/ and state assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1014-1029 (2005)
2004
118EEKanak Agarwal, Dennis Sylvester, David Blaauw: A simplified transmission-line based crosstalk noise model for on-chip RLC wiring. ASP-DAC 2004: 858-864
117EESanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: A stochastic approach To power grid analysis. DAC 2004: 171-176
116EESeokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge: Circuit-aware architectural simulation. DAC 2004: 305-310
115EEKanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula: Variational delay metrics for interconnect timing analysis. DAC 2004: 381-384
114EERajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Parametric yield estimation considering leakage variability. DAC 2004: 442-447
113EEAseem Agarwal, Florentin Dartu, David Blaauw: Statistical gate delay model considering multiple input switching. DAC 2004: 658-663
112EEDongwoo Lee, Vladimir Zolotov, David Blaauw: Static timing analysis using backward signal propagation. DAC 2004: 664-669
111EEAshish Srivastava, Dennis Sylvester, David Blaauw: Statistical optimization of leakage power considering process variations using dual-Vth and sizing. DAC 2004: 773-778
110EEHarmander Deogun, Rajeev R. Rao, Dennis Sylvester, David Blaauw: Leakage-and crosstalk-aware bus encoding for total power reduction. DAC 2004: 779-782
109EEAshish Srivastava, Dennis Sylvester, David Blaauw: Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. DAC 2004: 783-787
108EEBo Zhai, David Blaauw, Dennis Sylvester, Krisztián Flautner: Theoretical and practical limits of dynamic voltage scaling. DAC 2004: 868-873
107EEDongwoo Lee, Harmander Deogun, David Blaauw, Dennis Sylvester: Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization. DATE 2004: 494-499
106EEAshish Srivastava, Dennis Sylvester, David Blaauw: Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design. DATE 2004: 718-719
105EESeokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David Blaauw, Trevor N. Mudge: Reducing pipeline energy demands with local DVS and dynamic retiming. ISLPED 2004: 319-324
104EEWoo Hyung Lee, Sanjay Pant, David Blaauw: Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids. ISQED 2004: 131-136
103EETodd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner: Making Typical Silicon Matter with Razor. IEEE Computer 37(3): 57-65 (2004)
102EETodd M. Austin, David Blaauw, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Wayne Wolf: Mobile Supercomputers. IEEE Computer 37(5): 81-83 (2004)
101EEDan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner: Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. IEEE Micro 24(6): 10-20 (2004)
100 Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical analysis of subthreshold leakage current for VLSI circuits. IEEE Trans. VLSI Syst. 12(2): 131-139 (2004)
99 Dongwoo Lee, David Blaauw, Dennis Sylvester: Gate oxide leakage current analysis and reduction for VLSI circuits. IEEE Trans. VLSI Syst. 12(2): 155-166 (2004)
98 Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge: Circuit and microarchitectural techniques for reducing cache leakage power. IEEE Trans. VLSI Syst. 12(2): 167-184 (2004)
97EEKanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driver output model for on-chip RLC transmission lines. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 128-136 (2004)
96EEMurat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Postroute gate sizing for crosstalk noise reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1670-1677 (2004)
95EEAseem Agarwal, Vladimir Zolotov, David Blaauw: Statistical clock skew analysis considering intradie-process variations. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1231-1242 (2004)
94EEKanak Agarwal, Dennis Sylvester, David Blaauw: A simple metric for slew rate of RC circuits based on two circuit moments. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1346-1354 (2004)
2003
93EEJan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang: Reshaping EDA for power. DAC 2003: 15
92EEDongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester: Analysis and minimization techniques for total leakage considering gate oxide leakage. DAC 2003: 175-180
91EEDongwoo Lee, David Blaauw: Static leakage reduction through simultaneous threshold voltage and state assignment. DAC 2003: 191-194
90EEAseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Computation and Refinement of Statistical Bounds on Circuit Delay. DAC 2003: 348-353
89EEKanak Agarwal, Dennis Sylvester, David Blaauw: An effective capacitance based driver output model for on-chip RLC interconnects. DAC 2003: 376-381
88EEBhavana Thudi, David Blaauw: Non-iterative switching window computation for delay-noise. DAC 2003: 390-395
87EEKanak Agarwal, Dennis Sylvester, David Blaauw: Simple metrics for slew rate of RC circuits based on two circuit moments. DAC 2003: 950-953
86EEMurat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Post-route gate sizing for crosstalk noise reduction. DAC 2003: 954-957
85EEAseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical Timing Analysis Using Bounds. DATE 2003: 10062-10067
84EED. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David Blaauw, Rajendran Panda, Murat R. Becer, Alexandre Ardelea, A. Patel: SOI Transistor Model for Fast Transient Simulation. ICCAD 2003: 120128
83EESanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: Vectorless Analysis of Supply Noise Induced Delay Variation. ICCAD 2003: 184-192
82EESarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: AU: Timing Analysis Under Uncertainty. ICCAD 2003: 615-620
81EENam Sung Kim, David Blaauw, Trevor N. Mudge: Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches. ICCAD 2003: 627-632
80EEAseem Agarwal, David Blaauw, Vladimir Zolotov: Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations. ICCAD 2003: 900-907
79EEAseem Agarwal, David Blaauw, Vladimir Zolotov: Statistical Clock Skew Analysis Considering Intra-Die Process Variations. ICCAD 2003: 914-921
78EEShidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester: Optimal Inductance for On-chip RLC Interconnections. ICCD 2003: 264-
77EEHaitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) 2003: 668-671
76EERajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical estimation of leakage current considering inter- and intra-die process variation. ISLPED 2003: 84-89
75EEMurat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Post-Route Gate Sizing for Crosstalk Noise Reduction. ISQED 2003: 171-176
74EEDongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester: Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design. ISQED 2003: 287-292
73EEChanhee Oh, David Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta: Static Electromigration Analysis for Signal Interconnects. ISQED 2003: 377-
72EERobert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David Blaauw: An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages. ISVLSI 2003: 149-154
71EEDan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge: Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. MICRO 2003: 7-18
70EENam Sung Kim, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan: Leakage Current: Moore's Law Meets Static Power. IEEE Computer 36(12): 68-75 (2003)
69EERajendran Panda, Savithri Sundareswaran, David Blaauw: Impact of Low-Impedance Substrate on Power Supply Integrity. IEEE Design & Test of Computers 20(3): 16-22 (2003)
68EEDavid Blaauw, Supamas Sirichotiyakul, Chanhee Oh: Driver modeling and alignment for worst-case delay noise. IEEE Trans. VLSI Syst. 11(2): 157-166 (2003)
67EEDavid Blaauw, Chanhee Oh, Vladimir Zolotov, Aurobindo Dasgupta: Static electromigration analysis for on-chip signal interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 39-48 (2003)
66EEHaitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 49-66 (2003)
65EEMurat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj: Early probabilistic noise estimation for capacitively coupled interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 337-345 (2003)
64EELi Ding, David T. Blaauw, Pinaki Mazumder: Accurate crosstalk noise modeling for early signal integrity analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 627-634 (2003)
63EEDavid T. Blaauw, Luciano Lavagno: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 962-963 (2003)
62EESarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul: Probabilistic analysis of interconnect coupling noise. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1188-1203 (2003)
61EEAseem Agarwal, Vladimir Zolotov, David T. Blaauw: Statistical timing analysis using bounds and selective enumeration. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1243-1260 (2003)
2002
60EEHimanshu Kaul, Dennis Sylvester, David Blaauw: Active shields: a new approach to shielding global wires. ACM Great Lakes Symposium on VLSI 2002: 112-117
59EESarma B. K. Vrudhula, David Blaauw, Supamas Sirichotiyakul: Estimation of the likelihood of capacitive coupling noise. DAC 2002: 653-658
58EEMurat R. Becer, Vladimir Zolotov, David Blaauw, Rajendran Panda, Ibrahim N. Hajj: Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . DATE 2002: 456-464
57EEHaitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: A precorrected-FFT method for simulating on-chip inductance. ICCAD 2002: 221-227
56EESarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: Estimation of signal arrival times in the presence of delay noise. ICCAD 2002: 418-422
55EEVladimir Zolotov, David Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy: Noise propagation and failure criteria for VLSI designs. ICCAD 2002: 587-594
54EELi Ding, David Blaauw, Pinaki Mazumder: Efficient crosstalk noise modeling using aggressor and tree reductions. ICCAD 2002: 595-600
53EESteven M. Martin, Krisztián Flautner, Trevor N. Mudge, David Blaauw: Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. ICCAD 2002: 721-725
52EEKrisztián Flautner, Nam Sung Kim, Steven M. Martin, David Blaauw, Trevor N. Mudge: Drowsy Caches: Simple Techniques for Reducing Leakage Power. ISCA 2002: 148-157
51EELi Ding, Pinaki Mazumder, David Blaauw: Crosstalk noise estimation using effective coupling capacitance. ISCAS (5) 2002: 645-648
50EEAshish Srivastava, Robert Bai, David Blaauw, Dennis Sylvester: Modeling and analysis of leakage power considering within-die process variations. ISLPED 2002: 64-67
49EEMurat R. Becer, Rajendran Panda, David Blaauw, Ibrahim N. Hajj: Pre-route Noise Estimation in Deep Submicron Integrated Circuits. ISQED 2002: 413-418
48EEVladimir Zolotov, David Blaauw, Rajendran Panda, Chanhee Oh: Noise Injection and Propagation in High Performance Designs. ISQED 2002: 425-430
47EEAlexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh: False-Noise Analysis Using Resolution Method. ISQED 2002: 437-
46EENam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge: Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. MICRO 2002: 219-230
45EEFadi A. Aloul, Soha Hassoun, Karem A. Sakallah, David Blaauw: Robust SAT-Based Search Algorithm for Leakage Power Reduction. PATMOS 2002: 167-177
44EEMurat R. Becer, David Blaauw, Ibrahim N. Hajj, Rajendran Panda: Early probabilistic noise estimation for capacitively coupled interconnects. SLIP 2002: 77-83
43EEAseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 16-21
42EEAseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 29-36
41EEKanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driving point model for on-chip RLC interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 63-69
40EEBhavana Thudi, David Blaauw: Efficient switching window computation for cross-talk noise. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 84-91
39EEHimanshu Kaul, Dennis Sylvester, David Blaauw: Active shielding of RLC global interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 98-104
38EEAlexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov: False-noise analysis using logic implications. ACM Trans. Design Autom. Electr. Syst. 7(3): 474-498 (2002)
37EEDavid Blaauw, Luciano Lavagno: Guest Editors' Introduction: Hot Topics at This Year's Design Automation Conference. IEEE Design & Test of Computers 19(4): 72-73 (2002)
36EESupamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David Blaauw: Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits. IEEE Trans. VLSI Syst. 10(2): 79-90 (2002)
35EEKaushik Gala, David Blaauw, Vladimir Zolotov, P. M. Vaidya, A. Joshi: Inductance model and analysis methodology for high-speed on-chip interconnect. IEEE Trans. VLSI Syst. 10(6): 730-745 (2002)
34EEDavid T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran: Slope propagation in static timing analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1180-1195 (2002)
33EEMin Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw: Hierarchical analysis of power distribution networks. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 159-168 (2002)
32EEDavid Blaauw, Steven M. Martin, Trevor N. Mudge, Krisztián Flautner: Leakage Current Reduction in VLSI Systems. Journal of Circuits, Systems, and Computers 11(6): 621-636 (2002)
2001
31EEKaushik Gala, David Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao: Inductance 101: Analysis and Design Issues. DAC 2001: 329-334
30EESupamas Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo: Driver Modeling and Alignment for Worst-Case Delay Noise. DAC 2001: 720-725
29EEAlexey Glebov, Sergey Gavrilov, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov: False-Noise Analysis using Logic Implications. ICCAD 2001: 515-
28EERajendran Panda, Savithri Sundareswaran, David Blaauw: On the interaction of power distribution network with substrate. ISLPED 2001: 388-393
27EEDavid Blaauw, Rajendran Panda: On-Chip Inductance Extraction and Modelin. ISQED 2001: 14
26EEMurat R. Becer, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj: A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. ISQED 2001: 158-
2000
25 David Blaauw, Christian C. Enz, Thaddeus Gabara, Enrico Macii: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000 ACM 2000
24EEDavid Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang: On-chip inductance modeling. ACM Great Lakes Symposium on VLSI 2000: 75-80
23EEMin Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David Blaauw: Hierarchical analysis of power distribution networks. DAC 2000: 150-155
22EERajat Chaudhry, David Blaauw, Rajendran Panda, Tim Edwards: Current signature compression for IR-drop analysis. DAC 2000: 162-167
21EERafi Levy, David Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov: ClariNet: a noise analysis tool for deep submicron design. DAC 2000: 233-238
20EEDavid Blaauw, Rajendran Panda, Abhijit Das: Removing user specified false paths from timing graphs. DAC 2000: 270-273
19EEKaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David Blaauw: On-chip inductance modeling and analysis. DAC 2000: 63-68
18 David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda: Slope Propagation in Static Timing Analysis. ICCAD 2000: 338-343
17EERajendran Panda, David Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju: Model and analysis for combined package and on-chip power grid simulation. ISLPED 2000: 179-184
16EERajat Chaudhry, Rajendran Panda, Tim Edwards, David Blaauw: Design and Analysis of Power Distribution Networks with Accurate RLC Models. VLSI Design 2000: 151-155
1999
15 Farid N. Najm, Jason Cong, David Blaauw: Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999 ACM 1999
14EESupamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David Blaauw: Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. DAC 1999: 436-441
13EESavithri Sundareswaran, David Blaauw, Abhijit Dharchoudhury: A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. VLSI Design 1999: 175-180
1998
12EERajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David Blaauw: Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. DAC 1998: 388-391
11EEAbhijit Dharchoudhury, Rajendran Panda, David Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden: Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. DAC 1998: 738-743
10EEDavid Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards: Emerging power management tools for processor design. ISLPED 1998: 143-148
1997
9EESergey Gavrilov, Alexey Glebov, S. Rusakov, David Blaauw, Larry G. Jones, Gopalakrishnan Vijayan: Fast power loss calculation for digital static CMOS circuits. ED&TC 1997: 411-415
8EESergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David Blaauw: Library-less synthesis for static CMOS combinational logic circuits. ICCAD 1997: 658-662
7 Abhijit Dharchoudhury, David Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning: Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. ICCD 1997: 143-148
1995
6EEAlexey Glebov, David Blaauw, Larry G. Jones: Transistor reordering for low power CMOS gates using an SP-BDD representation. ISLPD 1995: 161-166
1994
5EELarry G. Jones, David Blaauw: A cache-based method for accelerating switch-level simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 211-218 (1994)
1990
4EEDavid T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham: Derivation of signal flow for switch-level simulation. EURO-DAC 1990: 301-305
3 David Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham: SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. ICCAD 1990: 66-69
2EEDaniel G. Saab, Robert B. Mueller-Thuns, David Blaauw, Joseph T. Rahmeh, Jacob A. Abraham: Hierarchical multi-level fault simulation of large systems. J. Electronic Testing 1(2): 139-149 (1990)
1989
1EEDavid Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh: Automatic Generation of Behavioral Models from Switch-Level Descriptions. DAC 1989: 179-184

Coauthor Index

1Jacob A. Abraham [1] [2] [3] [4]
2Aseem Agarwal [42] [43] [61] [79] [80] [85] [90] [95] [113] [137] [140] [168]
3Kanak Agarwal [41] [78] [87] [89] [94] [97] [115] [118] [139] [142] [146] [149] [150] [191] [200]
4Mridul Agarwal [142] [149]
5Robert C. Aitken (Rob Aitken) [207]
6Fabio Albano [194]
7Ilan Algor [75] [86] [96]
8Fadi A. Aloul [45]
9Charles J. Alpert [128]
10Alexandre Ardelea [84]
11Todd M. Austin [70] [71] [101] [102] [103] [105] [116] [125] [131] [136] [141] [144] [169]
12Robert Bai [50] [72]
13Prithviraj Banerjee (Prith Banerjee) [3]
14David Bearden [11]
15Murat R. Becer [26] [44] [49] [55] [58] [65] [73] [75] [84] [86] [96] [176] [181]
16Kerry Bernstein [93] [153]
17Valeria Bertacco [116] [144] [203] [204]
18Sarvesh Bhardwaj [56] [82] [120]
19Gabi Braca [21]
20Andres Bryant [153] [156]
21David Bull [207]
22Yu Cao [160]
23Chaitali Chakrabarti [102]
24Leland Chang [153]
25Rajat Chaudhry [16] [17] [22] [23]
26Gregory K. Chen [178] [188] [203]
27Eli Chiprout [167]
28Kaviraj Chopra [135] [137] [138] [140] [160] [163] [164] [166] [168] [176] [181] [183] [185] [195] [198]
29Brian Cline [160] [191] [196] [198] [200]
30Jason Cong [15]
31Florentin Dartu [113]
32Abhijit Das [20]
33Koushik K. Das [153]
34Shidhartha Das [71] [78] [101] [105] [116] [207]
35Aurobindo Dasgupta [21] [67] [73]
36Andrew DeOrio [203] [204]
37Harmander Deogun [107] [110] [121] [126]
38Anirudh Devgan [114] [124] [145] [146] [148]
39Abhijit Dharchoudhury [7] [8] [10] [11] [12] [13] [14]
40Li Ding [51] [54] [64] [206]
41Stephen W. Director [139]
42Ronald G. Dreslinski [171] [175] [188] [202]
43J. Dunning [7]
44Tim Edwards [10] [12] [14] [16] [22] [23] [36]
45Y. Egorov [84]
46Christian C. Enz [25]
47Dan Ernst [71] [101]
48David Fick [202] [203] [204]
49Krisztián Flautner [32] [46] [52] [53] [70] [71] [98] [101] [103] [108] [122] [125] [188] [207]
50Jerry Frenkil [93]
51Thaddeus Gabara [25]
52Kaushik Gala [19] [24] [31] [35] [57] [66] [77]
53Ravikishore Gandikota [176] [181] [199] [206]
54Sergey Gavrilov [8] [9] [29] [38] [47] [84]
55Joao Geada [176]
56Alexey Glebov [6] [8] [9] [29] [38] [47] [84]
57Amir Grinshpon [21] [55]
58Wilfried Haensch [153]
59Ibrahim N. Hajj [26] [44] [49] [58] [65] [75] [86] [96]
60Scott Hanson [129] [153] [156] [157] [179] [180] [194]
61Razi-Ul Haque [194]
62Soha Hassoun [45]
63Ryan Helfand [131]
64Mark Horowitz [93]
65Haitian Hu [57] [66] [77]
66Jie S. Hu [70]
67Jin Hu [204]
68Mary Jane Irwin [70]
69Amit Jain [132] [147]
70Larry G. Jones [5] [6] [9]
71A. Joshi [35]
72Vivek Joshi [155] [177] [191] [196] [200]
73Mahmut T. Kandemir [70]
74Eric Karl [130] [152] [165] [187] [190]
75Himanshu Kaul [39] [60] [136] [169] [174]
76Nam Sung Kim [46] [52] [70] [71] [81] [98] [101] [123] [178]
77Ram Krishnamurthy [174]
78Sarvesh H. Kulkarni [72] [162] [184]
79Wesley Kwong [72] [74] [92]
80Luciano Lavagno [37] [63]
81Dongwoo Lee [74] [91] [92] [99] [107] [112] [119] [143] [151]
82Seokwoo Lee [101] [105] [116]
83Woo Hyung Lee [104]
84Rafi Levy [21] [26] [30] [55]
85Yu-Shiang Lin [194]
86Frank Liu [115]
87Junsheng Long [4]
88Enrico Macii [25]
89Scott A. Mahlke [102]
90Igor L. Markov [197]
91Steven M. Martin [32] [52] [53]
92Pinaki Mazumder [51] [54] [64]
93Michael Minuth [131] [141]
94S. C. Moore [8]
95Trevor N. Mudge [32] [46] [52] [53] [70] [71] [81] [98] [101] [102] [103] [105] [116] [123] [125] [136] [144] [165] [169] [171] [175] [178] [187] [188] [202]
96Robert B. Mueller-Thuns [1] [2] [3]
97D. Nadezhin [84]
98Farid N. Najm [15] [145]
99Mini Nanua [127] [154] [170] [172]
100Sani R. Nassif [115] [128]
101Leyla Nazhandali [131] [141]
102Wolfgang Nebel [93]
103Joe Norton [7] [12]
104Edward J. Nowak [153]
105Chanhee Oh [10] [14] [18] [21] [26] [29] [30] [36] [47] [48] [55] [67] [68] [73] [75] [86] [96] [127]
106Javin Olson [131] [141]
107Boaz Orshav [21]
108Rajendran Panda [8] [10] [11] [12] [14] [16] [17] [18] [19] [20] [22] [23] [24] [27] [28] [33] [36] [44] [47] [48] [49] [55] [57] [58] [65] [66] [69] [73] [75] [77] [83] [84] [86] [96] [117]
109Sanjay Pant [71] [83] [104] [117] [131] [134] [159] [167] [182]
110A. Patel [84]
111Toan Pham [71] [105]
112Satyamurthy Pullela [7] [8]
113Jan M. Rabaey [93]
114Joseph T. Rahmeh [1] [2]
115Ravi Ramaraju [17]
116Rajeev R. Rao [71] [76] [100] [110] [114] [121] [124] [128] [148] [155] [161] [164] [166]
117Anna Reeves [131]
118David Roberts [125]
119Steffen Rochel [205]
120S. Rusakov [9]
121Daniel G. Saab [1] [2] [3] [4]
122Karem A. Sakallah [45]
123Takayasu Sakurai [93]
124Sachin S. Sapatnekar [23] [33] [57] [66] [77]
125Ann Marie Sastry [194]
126Louis Scheffer [183]
127Jae-sun Seo [173] [174] [186] [197]
128Mingoo Seok [179] [180] [192]
129Saumil Shah [133] [135] [139] [185] [205]
130Dushyant Sharma [133]
131Prashant Singh [173] [186]
132Supamas Sirichotiyakul [10] [14] [21] [26] [29] [30] [36] [55] [59] [62] [68]
133Ashish Srivastava [50] [72] [76] [100] [106] [109] [111] [133] [135] [139] [183] [185]
134Savithri Sundareswaran [13] [18] [28] [34] [69] [83] [117] [198]
135D. M. Sylvester [184]
136Dennis Sylvester [39] [41] [50] [60] [72] [74] [76] [78] [87] [89] [92] [93] [94] [97] [99] [100] [106] [107] [108] [109] [110] [111] [114] [115] [118] [119] [121] [122] [124] [126] [128] [129] [130] [133] [135] [136] [139] [142] [143] [146] [148] [149] [150] [151] [152] [153] [155] [156] [157] [161] [162] [163] [164] [165] [166] [169] [171] [173] [174] [175] [176] [177] [178] [179] [180] [181] [185] [186] [187] [188] [189] [190] [191] [192] [193] [194] [195] [196] [197] [199] [200] [201] [202] [203] [204] [205]
137Peivand Tehrani [206]
138Bhavana Thudi [40] [88]
139Carlos Tokunaga [194]
140Andres Torres [198]
141Bogdan Tutuianu [11]
142P. M. Vaidya [35]
143Ravi Vaidyanathan [11]
144Vineeth Veetil [189] [201] [205]
145Gopalakrishnan Vijayan [8] [9]
146Narayanan Vijaykrishnan (Vijaykrishnan Narayanan) [70]
147Sarma B. K. Vrudhula [42] [43] [56] [59] [62] [82] [85] [90] [115] [120]
148Junfeng Wang [19] [24] [31]
149Xinlin Wang [156]
150Kensall Wise [194]
151Wayne Wolf [102]
152Andrew Yang [93]
153Brian Young [17] [19]
154Bo Zhai [108] [122] [129] [131] [141] [153] [156] [158] [163] [171] [175]
155Min Zhao [23] [31] [33] [57] [66] [77]
156Cheng Zhuo [193] [195]
157Conrad H. Ziesler [71]
158Vladimir Zolotov [17] [18] [19] [21] [24] [26] [29] [30] [31] [34] [35] [38] [42] [43] [47] [48] [55] [57] [58] [61] [66] [67] [73] [75] [77] [79] [80] [83] [84] [85] [86] [90] [95] [96] [112] [117] [132] [133] [140]
159Jingyan Zuo [14] [26] [30]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)