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Jinian Bian Vis

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*2009
42EEShujun Deng, Zhiqiu Kong, Jinian Bian, Yanni Zhao: Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraints. ASP-DAC 2009: 769-774
41EEJunbo Yu, Qiang Zhou, Jinian Bian: Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources. ASP-DAC 2009: 85-90
40EELiu Dawei, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong: Cell shifting aware of wirelength and overlap. ISQED 2009: 506-510
2008
39EEKang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto: HyMacs: hybrid memory access optimization based on custom-instruction scheduling. ACM Great Lakes Symposium on VLSI 2008: 89-94
38EEYanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian: Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC 2008: 370-375
37EEKang Zhao, Jinian Bian, Chenqian Jiang, Sheqin Dong, Satoshi Goto: Cache miss reduction through hardware-assisted loop optimization. CSCWD 2008: 129-134
36EEXing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong: MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. FPL 2008: 559-562
35EEOu He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng: A novel fixed-outline floorplanner with zero deadspace for hierarchical design. ICCAD 2008: 16-23
34EEKang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto: Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration. ISQED 2008: 321-324
33EEKun Tong, Jinian Bian, Haili Wang: A cooperative universal data model platform for the data-centric electronic system-level design. Advanced Engineering Informatics 22(3): 296-306 (2008)
32EEKang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto: Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design. IEICE Transactions 91-A(6): 1478-1487 (2008)
31EEKang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto: Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System. IEICE Transactions 91-A(9): 2456-2464 (2008)
2007
30EEOu He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong: An effective buffer planning algorithm for IP based fixed-outline SOC placement. ACM Great Lakes Symposium on VLSI 2007: 564-569
29EEHui Zhang, Jinian Bian: A Management System of Metropolis Energy Information. CSCWD 2007: 1066-1071
28EEKang Zhao, Jinian Bian, Sheqin Dong: A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. CSCWD 2007: 121-126
27EEShujun Deng, Jinian Bian, Weimin Wu, Xiaoqing Yang, Yanni Zhao: EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure. DAC 2007: 588-593
26EEZhipeng Liu, Jinian Bian, Qiang Zhou, Hui Dai: Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan. ISVLSI 2007: 279-284
25EEZhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng: Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 645-658 (2007)
2006
24EEKang Zhao, Jinian Bian: A Clustering ILP Model for Fast Instruction Selection in Embedded Applicated Specific Processor Design. APCCAS 2006: 1160-1163
23EELiang Zhu, Jinian Bian: From Software to Hardware - A Novel TLM Auto-Generating Method. APCCAS 2006: 1725-1728
22EEZhen Zhao, Jinian Bian, Zhipeng Liu, Yunfeng Wang, Kang Zhao: High Level Synthesis with Multiple supply Voltages for Energy and Combined Peak Power Minimization. APCCAS 2006: 864-867
21EEKun Tong, Jinian Bian, Haili Wang: Universal data model platform: the data-centric evolution for system level codesign. CSCWD 2006: 1037-1042
20EEYawen Niu, Jinian Bian, Haili Wang, Kun Tong, Liang Zhu: AGOM: A Novel Method of Embedded System Communication Architecture Design in System Level Design. CSCWD 2006: 324-329
19EEShujun Deng, Weimin Wu, Jinian Bian: Cooperative Bounded Model Checking Using STE and Hybrid Three-Valued SAT Solving. CSCWD 2006: 522-528
18EEYawen Niu, Jinian Bian, Haili Wang, Kun Tong: An Efficient Cooperative Design Framework for SOC On-Chip Communication Architecture System-Level Design. CSCWD (Selected Papers) 2006: 118-127
17EEShujun Deng, Weimin Wu, Jinian Bian: Bounded Model Checking Combining Symbolic Trajectory Evaluation Abstraction with Hybrid Three-Valued SAT Solving. CSCWD (Selected Papers) 2006: 297-307
16EEZhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng: Integrating dynamic thermal via planning with 3D floorplanning algorithm. ISPD 2006: 178-185
15EEKang Zhao, Jinian Bian, Sheqin Dong: A Heterogeneous Dependency Graph as Intermediate Representation for Instruction Set Customization. JCIS 2006
14EEZhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani: Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. ACM Trans. Design Autom. Electr. Syst. 11(2): 325-345 (2006)
13EEMing Zhu, Jinian Bian, Weimin Wu: A novel collaborative scheme of simulation and model checking for system properties verification. Computers in Industry 57(8-9): 752-757 (2006)
2005
12EEQiang Wu, Jinian Bian, Hongxi Xue: System-level architectural exploration using allocation-on-demand technique. ASP-DAC 2005: 1296-1298
11 Feng Lin, Haili Wang, Jinian Bian: HW/SW Interface Synthesis Based on Avalon Bus Specification for Nios-Oriented SoC Design. FPT 2005: 305-306
10EEYunfeng Wang, Jinian Bian, Xianlong Hong, Liu Yang, Qiang Zhou, Qiang Wu: A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. ICESS 2005: 275-286
9EEYunfeng Wang, Jinian Bian, Xianlong Hong: Interconnect delay optimization via high level re-synthesis after floorplanning. ISCAS (6) 2005: 5641-5644
8EEZhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani: A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. ISCAS (6) 2005: 6230-6233
2004
7EEJianzhou Zhao, Jinian Bian, Weimin Wu: PFGASAT- A Genetic SAT Solver Combining Partitioning and Fuzzy Strategie. COMPSAC 2004: 108-113
6EEQiang Wu, Jinian Bian, Hongxi Xue: A Distributed Architecture Model for Heterogeneous Multiprocessor System-on-Chip Design. ICESS 2004: 150-157
5EEMing Zhu, Jinian Bian, Weimin Wu: Model Optimization Techniques in a Verification Platform for Classified Properties. ICESS 2004: 542-548
4EEHaili Wang, Jinian Bian, Yawen Niu, Kun Tong, Yunfeng Wang: CA-Ex: A Tuning-Incremental Methodology for Communication Architectures in Embedded Systems. ICESS 2004: 74-80
2003
3EEMing Zhu, Jinian Bian, Weimin Wu, Hongxi Xue: Property Classification for Functional Verification Based. Asian Test Symposium 2003: 503
2000
2EEWangning Long, Yu-Liang Wu, Jinian Bian: IBAW: an implication-tree based alternative-wiring logic transformation algorithm. ASP-DAC 2000: 415-422
1999
1EEJinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong: FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking. ASP-DAC 1999: 363-

Coauthor Index

1Jinsong Bei [1]
2Yici Cai [8] [36] [38] [40]
3Juanjuan Chen [36]
4Chung-Kuan Cheng [16] [25] [35]
5Hui Dai [26]
6Liu Dawei [40]
7Shujun Deng [17] [19] [27] [42]
8Sheqin Dong [15] [28] [30] [31] [32] [34] [35] [37] [39]
9Satoshi Goto [31] [32] [34] [35] [37] [39]
10Ou He [30] [35]
11Xianlong Hong [1] [8] [9] [10] [14] [16] [25] [30] [36] [38] [40]
12Jiang Hu [38]
13Chenqian Jiang [37]
14Zhiqiu Kong [42]
15Hongxing Li [1]
16Zhuoyuan Li [8] [14] [16] [25]
17Feng Lin [11]
18Zhipeng Liu [22] [26]
19Wangning Long [2]
20Yuchun Ma [30]
21Yawen Niu [4] [18] [20]
22Vijay Pitchumani [8] [14] [16] [25]
23Prashant Saxena [8]
24Yang Song [31] [32] [34] [39]
25Kun Tong [4] [18] [20] [21] [33]
26Haili Wang [4] [11] [18] [20] [21] [33]
27Yanfeng Wang [38]
28Yunfeng Wang [4] [9] [10] [22]
29Xing Wei [36]
30Qiang Wu [6] [10] [12]
31Weimin Wu [3] [5] [7] [13] [17] [19] [27]
32Yu-Liang Wu (David Yu-Liang Wu) [2]
33Hongxi Xue [1] [3] [6] [12]
34Hannah Honghua Yang (Honghua Yang) [14] [16] [25]
35Hannal Yang [8]
36Liu Yang [10]
37Xiaoqing Yang [27]
38Junbo Yu [41]
39Wenjian Yu [25]
40Shan Zeng [16] [25]
41Hui Zhang [29]
42Jianzhou Zhao [7]
43Kang Zhao [15] [22] [24] [28] [31] [32] [34] [37] [39]
44Yanni Zhao [27] [42]
45Zhen Zhao [22]
46Qiang Zhou [8] [10] [14] [16] [25] [26] [36] [38] [40] [41]
47Liang Zhu [20] [23]
48Ming Zhu [3] [5] [13]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)