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Swarup Bhunia Vis

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*2009
81EERajat Subhra Chakraborty, Francis G. Wolff, Somnath Paul, Christos A. Papachristou, Swarup Bhunia: MERO: A Statistical Approach for Hardware Trojan Detection. CHES 2009: 396-410
80EERajat Subhra Chakraborty, Swarup Bhunia: A study of asynchronous design methodology for robust CMOS-nano hybrid system design. JETC 5(3): (2009)
2008
79EEMatthew Seetharam A. Holtz, Seetharam Narasimhan, Swarup Bhunia: On-die CMOS voltage droop detection and dynamiccompensation. ACM Great Lakes Symposium on VLSI 2008: 35-40
78EESomnath Paul, Swarup Bhunia: MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices. ASP-DAC 2008: 77-82
77EESeetharam Narasimhan, Somnath Paul, Swarup Bhunia: Collective computing based on swarm intelligence. DAC 2008: 349-350
76EESomnath Paul, Swarup Bhunia: Reconfigurable computing using content addressable memory for improved performance and resource usage. DAC 2008: 786-791
75EEFrancis G. Wolff, Christos A. Papachristou, Swarup Bhunia, Rajat Subhra Chakraborty: Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme. DATE 2008: 1362-1365
74EELawrence Leinweber, Swarup Bhunia: Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction. DATE 2008: 373-378
73EEYu Zhou, Somnath Paul, Swarup Bhunia: Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement. DATE 2008: 98-103
72EERajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia: On-Demand Transparency for Improving Hardware Trojan Detectability. HOST 2008: 48-50
71EESomnath Paul, Saibal Mukhopadhyay, Swarup Bhunia: Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches. ICCAD 2008: 589-592
70EERajat Subhra Chakraborty, Swarup Bhunia: Hardware protection and authentication through netlist level obfuscation. ICCAD 2008: 674-677
69EESwarup Bhunia, Kaushik Roy: Low power design under parameter variations. ISLPED 2008: 137-138
68EERajat Subhra Chakraborty, Swarup Bhunia: Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar. ISQED 2008: 697-701
67EEYu Zhou, Somnath Paul, Swarup Bhunia: Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect. ISQED 2008: 861-866
66EESwarup Bhunia, Kaushik Roy: Low power design under parameter variations. SoCC 2008: 389-390
65EERajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia: Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits. VLSI Design 2008: 441-446
64EEPatrick Ndai, Swarup Bhunia, Amit Agarwal, Kaushik Roy: Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput. IEEE Trans. Computers 57(7): 940-951 (2008)
63EEAnimesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy: Profit Aware Circuit Design Under Process Variations Considering Speed Binning. IEEE Trans. VLSI Syst. 16(7): 806-815 (2008)
62EESwarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy: Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. J. Electronic Testing 24(6): 577-590 (2008)
2007
61EESwarup Bhunia, Massood Tabib-Azar, Daniel G. Saab: Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches. ASP-DAC 2007: 86-91
60EESwaroop Ghosh, Swarup Bhunia, Kaushik Roy: Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling. DATE 2007: 1532-1537
59EESomnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia: Low-overhead design technique for calibration of maximum frequency at multiple operating points. ICCAD 2007: 401-404
58EESomnath Paul, Swarup Bhunia: Memory based computation using embedded cache for processor yield and reliability improvement. ICCD 2007: 341-346
57EESwaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy: Tolerance to Small Delay Defects by Adaptive Clock Stretching. IOLTS 2007: 244-252
56EESomnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia: Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield. IOLTS 2007: 29-36
55EEYu Zhou, Shijo Thekkel, Swarup Bhunia: Low power FPGA design using hybrid CMOS-NEMS approach. ISLPED 2007: 14-19
54EESivasubramaniam Krishnamurthy, Somnath Paul, Swarup Bhunia: Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration. ISQED 2007: 755-760
53EESwarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: Process Variations and Process-Tolerant Design. VLSI Design 2007: 699-704
52EESomnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia: VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips. VTS 2007: 455-460
51EESwaroop Ghosh, Swarup Bhunia, Kaushik Roy: Low-Power and testable circuit synthesis using Shannon decomposition. ACM Trans. Design Autom. Electr. Syst. 12(4): (2007)
50EEAnimesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy: Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies CoRR abs/0710.4663: (2007)
49EESaibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits CoRR abs/0710.4729: (2007)
48EEAmit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy: Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies. IEEE Trans. VLSI Syst. 15(6): 660-671 (2007)
47EESwaroop Ghosh, Swarup Bhunia, Kaushik Roy: CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1947-1956 (2007)
2006
46EEAshish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy: Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. ASP-DAC 2006: 665-670
45EEAnimesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy: Speed binning aware design methodology to improve profit under parameter variations. ASP-DAC 2006: 712-717
44EEArijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy: Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. DATE 2006: 856-861
43EENilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia: Low power synthesis of dynamic logic circuits using fine-grained clock gating. DATE 2006: 862-867
42EESwaroop Ghosh, Swarup Bhunia, Kaushik Roy: A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. ICCAD 2006: 619-624
41EESwaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. IOLTS 2006: 31-36
40EENilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi: Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. IEEE Trans. VLSI Syst. 14(9): 1034-1039 (2006)
39EEAnimesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2427-2436 (2006)
38EESwaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2934-2943 (2006)
37EESaibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1486-1495 (2006)
2005
36EEAnimesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. Asian Test Symposium 2005: 170-175
35EESwaroop Ghosh, Swarup Bhunia, Kaushik Roy: Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. Asian Test Symposium 2005: 404-409
34EESwarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy: A novel synthesis approach for active leakage power reduction using dynamic supply gating. DAC 2005: 479-484
33EESwarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy: A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. DATE 2005: 1136-1141
32EESaibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. DATE 2005: 224-229
31EEAnimesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy: Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. DATE 2005: 926-931
30EENilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy: Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. ICCD 2005: 206-214
29EEAnimesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. IOLTS 2005: 275-280
28EEAmit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy: Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations. ISLPED 2005: 14-19
27EEAnimesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. ISQED 2005: 358-363
26EESwarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy: Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. ISQED 2005: 453-458
25EEQikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy: Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. VTS 2005: 292-297
24EELih-Yih Chiou, Swarup Bhunia, Kaushik Roy: Synthesis of application-specific highly efficient multi-mode cores for embedded systems. ACM Trans. Embedded Comput. Syst. 4(1): 168-188 (2005)
23EESwarup Bhunia, Animesh Datta, Nilanjan Banerjee, Kaushik Roy: GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. IEEE Trans. Computers 54(6): 752-766 (2005)
22EEArijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy: Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation. IEEE Trans. VLSI Syst. 13(11): 1213-1224 (2005)
21EEQikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy: Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. IEEE Trans. VLSI Syst. 13(11): 1286-1295 (2005)
20EESwarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy: Low-power scan design using first-level supply gating. IEEE Trans. VLSI Syst. 13(3): 384-395 (2005)
19EESwarup Bhunia, Kaushik Roy: A novel wavelet transform-based transient current analysis for fault detection and localization. IEEE Trans. VLSI Syst. 13(4): 503-507 (2005)
18EESwarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current. J. Electronic Testing 21(2): 147-159 (2005)
17EESwarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. J. Electronic Testing 21(3): 243-255 (2005)
2004
16EESwarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis. DATE 2004: 704-705
15EESwarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy: First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. DFT 2004: 314-315
14EESwarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy: A Novel Low-Power Scan Design Technique Using Supply Gating. ICCD 2004: 60-65
13EEDebjyoti Ghosh, Swarup Bhunia, Kaushik Roy: A Technique to Reduce Power and Test Application Time in BIST. IOLTS 2004: 182-183
12EESwarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. ISQED 2004: 389-394
11 Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar: DCG: deterministic clock-gating for low-power microprocessor design. IEEE Trans. VLSI Syst. 12(3): 245-254 (2004)
2003
10EELih-Yih Chiou, Swarup Bhunia, Kaushik Roy: Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications. DATE 2003: 10096-10103
9EEDebjyoti Ghosh, Swarup Bhunia, Kaushik Roy: Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST. DFT 2003: 191-198
8EEHai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy: Deterministic Clock Gating for Microprocessor Power Reduction. HPCA 2003: 113-
2002
7EESwarup Bhunia, Hai Li, Kaushik Roy: A High Performance IDDQ Testable Cache for Scaled CMOS Technologies. Asian Test Symposium 2002: 157-
6EESwarup Bhunia, Kaushik Roy, Jaume Segura: A novel wavelet transform based transient current analysis for fault detection and localization. DAC 2002: 361-366
5EESwarup Bhunia, Kaushik Roy: Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis. DATE 2002: 1118
4 Arijit Bishnu, Swarup Bhunia, C. A. Murthy, Bhargab B. Bhattacharya, Malay Kumar Kundu, Tinku Acharya: Content based image retrieval: related issues using Euler vector. ICIP (2) 2002: 585-588
3EESwarup Bhunia, Kaushik Roy: Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform. VTS 2002: 302-310
2000
2EESwarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya: Topological Routing Amidst Polygonal Obstacles. VLSI Design 2000: 274-279
1999
1EESwarup Bhunia, Soumya K. Ghosh, Pramod Kumar, Partha Pratim Das, Jayanta Mukherjee: Design, Simulation and Synthesis of an ASIC for Fractal Image Compression. VLSI Design 1999: 544-547

Coauthor Index

1Tinku Acharya [4]
2Amit Agarwal [28] [48] [64]
3Nilanjan Banerjee [23] [27] [30] [31] [34] [40] [43] [50]
4Bhargab B. Bhattacharya [2] [4]
5Arijit Bishnu [4]
6Rajat Subhra Chakraborty [52] [56] [65] [68] [70] [72] [75] [80] [81]
7Qikai Chen [21] [25] [34]
8Yiran Chen [8] [11]
9Lih-Yih Chiou [10] [24]
10Jung Hwan Choi [45] [63]
11Partha Pratim Das [1]
12Animesh Datta [23] [27] [29] [31] [36] [39] [45] [50] [63]
13James D. Gallagher [28] [48]
14Debjyoti Ghosh [9] [13] [14] [20] [26]
15Soumya K. Ghosh [1]
16Swaroop Ghosh [35] [38] [41] [42] [47] [51] [57] [60]
17Ashish Goel [46]
18Matthew Seetharam A. Holtz [79]
19Kunhyuk Kang [28] [48]
20Sivasubramaniam Krishnamurthy [54] [59]
21Pramod Kumar [1]
22Malay Kumar Kundu (Malay K. Kundu) [4]
23Lawrence Leinweber [74]
24Hai Li [7] [8] [11]
25Hamid Mahmoodi (Hamid Mahmoodi-Meimand) [14] [15] [20] [21] [25] [26] [30] [33] [34] [40] [43] [46] [59] [62]
26Subhashis Majumder [2]
27Jayanta Mukherjee [1]
28Saibal Mukhopadhyay [14] [20] [29] [31] [32] [36] [37] [39] [45] [49] [50] [53] [63] [71]
29C. A. Murthy [4]
30Seetharam Narasimhan [77] [79]
31Patrick Ndai [57] [64]
32Christos A. Papachristou [75] [81]
33Bipul Chandra Paul (Bipul C. Paul) [22] [44]
34Somnath Paul [52] [54] [56] [58] [59] [65] [67] [71] [72] [73] [76] [77] [78] [81]
35Arijit Raychowdhury [12] [15] [16] [17] [18] [22] [30] [33] [38] [40] [41] [44] [62]
36Kaushik Roy [3] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [53] [57] [60] [62] [63] [64] [66] [69]
37Daniel G. Saab [61]
38Jaume Segura [6]
39Ayan Sircar [2]
40Susmita Sur-Kolay [2]
41Massood Tabib-Azar [61]
42Shijo Thekkel [55]
43T. N. Vijaykumar [8] [11]
44Francis G. Wolff [75] [81]
45Yu Zhou [55] [67] [73]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)