| * | 2009 |
| 20 | EE | Jean-Luc Beuchat,
Jérémie Detrey,
Nicolas Estibals,
Eiji Okamoto,
Francisco Rodríguez-Henríquez:
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers.
CHES 2009: 225-239 |
| 2008 |
| 19 | EE | Jean-Luc Beuchat,
Nicolas Brisebarre,
Jérémie Detrey,
Eiji Okamoto,
Francisco Rodríguez-Henríquez:
A Comparison between Hardware Accelerators for the Modified Tate Pairing over F2m and F3m.
Pairing 2008: 297-315 |
| 18 | EE | Jean-Luc Beuchat,
Nicolas Brisebarre,
Jérémie Detrey,
Eiji Okamoto,
Masaaki Shirase,
Tsuyoshi Takagi:
Algorithms and Arithmetic Operators for Computing the etaT Pairing in Characteristic Three.
IEEE Trans. Computers 57(11): 1454-1468 (2008) |
| 17 | EE | Jean-Luc Beuchat,
Jean-Michel Muller:
Automatic Generation of Modular Multipliers for FPGA Applications.
IEEE Trans. Computers 57(12): 1600-1613 (2008) |
| 2007 |
| 16 | EE | Jean-Luc Beuchat,
Takanori Miyoshi,
Yoshihito Oyama,
Eiji Okamoto:
Multiplication over Fpm on FPGA: A Survey.
ARC 2007: 214-225 |
| 15 | EE | Jean-Luc Beuchat,
Nicolas Brisebarre,
Jérémie Detrey,
Eiji Okamoto:
Arithmetic Operators for Pairing-Based Cryptography.
CHES 2007: 239-255 |
| 14 | EE | Jean-Luc Beuchat,
Masaaki Shirase,
Tsuyoshi Takagi,
Eiji Okamoto:
An Algorithm for the nt Pairing Calculation in Characteristic Three and its Hardware Implementation.
IEEE Symposium on Computer Arithmetic 2007: 97-104 |
| 13 | EE | Jean-Luc Beuchat,
Nicolas Brisebarre,
Masaaki Shirase,
Tsuyoshi Takagi,
Eiji Okamoto:
A Coprocessor for the Final Exponentiation of the eta T Pairing in Characteristic Three.
WAIFI 2007: 25-39 |
| 12 | EE | Jean-Luc Beuchat:
Further Comments on ``Residue-to-Binary Converters Based on New Chinese Remainder Theorems''
CoRR abs/0707.3732: (2007) |
| 2005 |
| 11 | EE | Jean-Luc Beuchat,
Jean-Michel Muller:
Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement.
ASAP 2005: 303-308 |
| 2004 |
| 10 | | Jean-Luc Beuchat,
Arnaud Tisserand:
Évaluation polynomiale en-ligne de fonctions élémentaires sur FPGA.
Technique et Science Informatiques 23(10): 1247-1267 (2004) |
| 2003 |
| 9 | EE | Jean-Luc Beuchat:
FPGA Implementations of the RC6 Block Cipher.
FPL 2003: 101-110 |
| 8 | EE | Jean-Luc Beuchat:
Some Modular Adders and Multipliers for Field Programmable Gate Arrays.
IPDPS 2003: 190 |
| 2002 |
| 7 | EE | Jean-Luc Beuchat,
Arnaud Tisserand:
Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices.
FPL 2002: 513-522 |
| 6 | EE | Jean-Luc Beuchat,
Jacques-Olivier Haenni,
Héctor Fabio Restrepo,
Christof Teuscher,
Francesco J. Gómez,
Eduardo Sanchez:
Approches matérielles et logicielles de l'algorithme de chiffrement IDEA.
Technique et Science Informatiques 21(2): 203-224 (2002) |
| 1999 |
| 5 | | Jean-Luc Beuchat,
Eduardo Sanchez:
An On-Line Arithmetic-Based Reconfigurable Neuroprocessor.
IPPS/SPDP Workshops 1999: 700-702 |
| 4 | EE | Jean-Luc Beuchat,
Eduardo Sanchez:
Using On-Line Arithmetic and Reconfiguration for Neuroprocessor Implementations.
IWANN (2) 1999: 129-138 |
| 3 | | Eduardo Sanchez,
Moshe Sipper,
Jacques-Olivier Haenni,
Jean-Luc Beuchat,
André Stauffer,
Andrés Pérez-Uribe:
Static and Dynamic Configurable Systems.
IEEE Trans. Computers 48(6): 556-564 (1999) |
| 1998 |
| 2 | EE | Jacques-Olivier Haenni,
Jean-Luc Beuchat,
Eduardo Sanchez:
RENCO: A Reconfigurable Network Computer.
FCCM 1998: 288-289 |
| 1 | | Jean-Luc Beuchat,
Jacques-Olivier Haenni,
Eduardo Sanchez:
Hardware Reconfigurable Neural Networks.
IPPS/SPDP Workshops 1998: 91-98 |