| 2008 |
|---|
| 54 | | Fabien Soulier,
Lionel Gouyet,
Guy Cathébras,
Serge Bernard,
David Guiraud,
Yves Bertrand:
Considerations on Improving the Design of CUFF Electrode for ENG Recording - Geometrical Approach, Dedicated IC, Sensitivity, Noise Rejection.
BIODEVICES (2) 2008: 180-185 |
| 2007 |
|---|
| 53 | EE | Mehdi Baba-ali,
David Marcheix,
Xavier Skapin,
Yves Bertrand:
Generic computation of bulletin boards into geometric kernels.
Afrigraph 2007: 85-93 |
| 52 | | Sebastien Horna,
Guillaume Damiand,
Daniel Meneveaux,
Yves Bertrand:
Building 3D indoor scenes topology from 2D architectural plans.
GRAPP (GM/R) 2007: 37-44 |
| 2005 |
|---|
| 51 | EE | Jean Marc Galliere,
Michel Renovell,
Florence Azaïs,
Yves Bertrand:
Delay Testing Viability of Gate Oxide Short Defects.
J. Comput. Sci. Technol. 20(2): 195-200 (2005) |
| 50 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Mariane Comte,
Michel Renovell:
Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications.
J. Electronic Testing 21(3): 291-298 (2005) |
| 49 | EE | Sylvain Prat,
Patrick Gioia,
Yves Bertrand,
Daniel Meneveaux:
Connectivity compression in an arbitrary dimension.
The Visual Computer 21(8-10): 876-885 (2005) |
| 2004 |
|---|
| 48 | EE | Marie-Lise Flottes,
Yves Bertrand,
L. Balado,
E. Lupon,
Anton Biasizzo,
Franc Novak,
Stefano Di Carlo,
Paolo Prinetto,
N. Pricopi,
Hans-Joachim Wunderlich:
Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ.
DELTA 2004: 135-139 |
| 47 | EE | Guillaume Damiand,
Yves Bertrand,
Christophe Fiorio:
Topological model for two-dimensional image representation: definition and optimal extraction algorithm.
Computer Vision and Image Understanding 93(2): 111-154 (2004) |
| 2003 |
|---|
| 46 | EE | Michel Renovell,
Jean Marc Galliere,
Florence Azaïs,
Yves Bertrand:
Delay Testing of MOS Transistor with Gate Oxide Short.
Asian Test Symposium 2003: 168-173 |
| 45 | EE | Serge Bernard,
Mariane Comte,
Florence Azaïs,
Yves Bertrand,
Michel Renovell:
A New Methodology For ADC Test Flow Optimization.
ITC 2003: 201-209 |
| 44 | EE | Yves Bertrand,
Marie-Lise Flottes,
L. Balado,
Joan Figueras,
Anton Biasizzo,
Franc Novak,
Stefano Di Carlo,
Paolo Prinetto,
N. Pricopi,
Hans-Joachim Wunderlich,
J.-P. Van der Heyden:
Test Engineering Education in Europe: the EuNICE-Test Project.
MSE 2003: 85-86 |
| 43 | EE | Florence Azaïs,
Yves Bertrand,
Michel Renovell,
André Ivanov,
Sassan Tabatabaei:
An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs.
IEEE Design & Test of Computers 20(1): 60-67 (2003) |
| 42 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Mariane Comte,
Michel Renovell:
A-to-D converters static error detection from dynamic parameter measurement.
Microelectronics Journal 34(10): 945-953 (2003) |
| 2002 |
|---|
| 41 | EE | Vincent Beroulle,
Yves Bertrand,
Laurent Latorre,
Pascal Nouet:
On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems.
DATE 2002: 1120 |
| 40 | EE | Yves Bertrand,
Marie-Lise Flottes,
Florence Azaïs,
Serge Bernard,
Laurent Latorre,
Regis Lorival:
European Network for Test Education.
DELTA 2002: 230-234 |
| 39 | EE | Vincent Beroulle,
Yves Bertrand,
Laurent Latorre,
Pascal Nouet:
Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical Systems.
VTS 2002: 439-444 |
| 38 | EE | Michel Renovell,
Florence Azaïs,
Yves Bertrand:
Improving Defect Detection in Static-Voltage Testing.
IEEE Design & Test of Computers 19(6): 83-89 (2002) |
| 37 | EE | Franck Ledoux,
Jean-Marc Mota,
Agnès Arnould,
Catherine Dubois,
Pascale Le Gall,
Yves Bertrand:
Spécifications formelles du chanfreinage.
Technique et Science Informatiques 21(8): 1073-1098 (2002) |
| 2001 |
|---|
| 36 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Michel Renovell:
Implementation of a linear histogram BIST for ADCs.
DATE 2001: 590-595 |
| 35 | EE | Serge Bernard,
Florence Azaïs,
Yves Bertrand,
Michel Renovell:
Analog BIST Generator for ADC Testing.
DFT 2001: 338-346 |
| 34 | | Michel Renovell,
Jean Marc Galliere,
Florence Azaïs,
Serge Bernard,
Yves Bertrand:
Boolean and current detection of MOS transistor with gate oxide short.
ITC 2001: 1039-1048 |
| 33 | | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Michel Renovell:
On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST.
VLSI-SOC 2001: 425-436 |
| 32 | | Vincent Beroulle,
Yves Bertrand,
Laurent Latorre,
Pascal Nouet:
Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing.
VLSI-SOC 2001: 461-472 |
| 31 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Xavier Michel,
Michel Renovell:
A Low-Cost Adaptive Ramp Generator for Analog BIST Applications.
VTS 2001: 266-271 |
| 30 | EE | Franck Ledoux,
Agnès Arnould,
Pascale Le Gall,
Yves Bertrand:
Geometric Modelling with CASL.
WADT 2001: 176-200 |
| 29 | EE | Sylvain Thery,
Dominique Bechmann,
Yves Bertrand:
N-Dimensional Gregory-Bezier for N-Dimensional Cellular Complexes.
WSCG (Short Papers) 2001: 16-23 |
| 28 | EE | André Ivanov,
Sumbal Rafiq,
Michel Renovell,
Florence Azaïs,
Yves Bertrand:
On the detectability of CMOS floating gate transistor faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 116-128 (2001) |
| 2000 |
|---|
| 27 | EE | Luigi Carro,
Érika F. Cota,
Marcelo Lubaszewski,
Yves Bertrand,
Florence Azaïs,
Michel Renovell:
TI-BIST: a temperature independent analog BIST for switched-capacitor filters.
Asian Test Symposium 2000: 78-83 |
| 26 | EE | Érika F. Cota,
Michel Renovell,
Florence Azaïs,
Yves Bertrand,
Luigi Carro,
Marcelo Lubaszewski:
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte.
DATE 2000: 226- |
| 25 | EE | Yves Bertrand,
Guillaume Damiand,
Christophe Fiorio:
Topological Encoding of 3D Segmented Images.
DGCI 2000: 311-324 |
| 24 | EE | Michel Renovell,
Florence Azaïs,
Serge Bernard,
Yves Bertrand:
Hardware Resource Minimization for Histogram-Based ADC BIST.
VTS 2000: 247-254 |
| 23 | | Sylvain Brandel,
Dominique Bechmann,
Yves Bertrand:
Thickening: an operation for animation.
Journal of Visualization and Computer Animation 11(5): 261-277 (2000) |
| 22 | EE | Jean Françon,
Yves Bertrand:
Topological 3D-manifolds: a statistical study of the cells.
Theor. Comput. Sci. 234(1-2): 233-254 (2000) |
| 1999 |
|---|
| 21 | EE | Laurent Latorre,
Yves Bertrand,
P. Hazard,
F. Pressecq,
Pascal Nouet:
Design, Characterization & Modelling of a CMOS Magnetic Field Sensor.
DATE 1999: 239-243 |
| 20 | EE | Yves Bertrand,
Christophe Fiorio,
Yann Pennaneach:
Border Map: A Topological Representation for nD Image Analysis.
DGCI 1999: 242-257 |
| 19 | | Michel Renovell,
André Ivanov,
Yves Bertrand,
Florence Azaïs,
Sumbal Rafiq:
Optimal conditions for Boolean and current detection of floating gate faults.
ITC 1999: 477-486 |
| 18 | EE | Yves Bertrand,
Florence Azaïs,
Marie-Lise Flottes,
Regis Lorival:
A Successful Distance-Learning Experience for IC Test Education.
MSE 1999: 20-21 |
| 1998 |
|---|
| 17 | EE | Michel Renovell,
Florence Azaïs,
J-C. Bodin,
Yves Bertrand:
BISTing Switched-Current Circuits.
Asian Test Symposium 1998: 372-377 |
| 16 | EE | Florence Azaïs,
André Ivanov,
Michel Renovell,
Yves Bertrand:
A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs.
Asian Test Symposium 1998: 383-387 |
| 15 | EE | Michel Renovell,
Florence Azaïs,
Yves Bertrand:
Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits.
DATE 1998: 815-821 |
| 14 | EE | Florence Azaïs,
Michel Renovell,
Yves Bertrand,
J-C. Bodin:
Design-For-Testability for Switched-Current Circuits.
VTS 1998: 370-375 |
| 1997 |
|---|
| 13 | | Michel Renovell,
Yves Bertrand:
Test Strategy Sensitivity to Defect Parameters.
ITC 1997: 607-616 |
| 1996 |
|---|
| 12 | | Michel Renovell,
P. Huc,
Yves Bertrand:
The Logic Threshold Based Voting: A Model for Local Feedback Bridging Fault.
EDCC 1996: 205-213 |
| 11 | EE | Michel Renovell,
P. Huc,
Yves Bertrand:
Bridging fault coverage improvement by power supply control.
VTS 1996: 338-343 |
| 10 | EE | Michel Renovell,
Florence Azaïs,
Yves Bertrand:
The multi-configuration: A DFT technique for analog circuits.
VTS 1996: 54-59 |
| 1995 |
|---|
| 9 | EE | Michel Renovell,
P. Huc,
Yves Bertrand:
Serial transistor network modeling for bridging fault simulation.
Asian Test Symposium 1995: 100-106 |
| 8 | EE | Michel Renovell,
Florence Azaïs,
Yves Bertrand:
A design-for-test technique for multistage analog circuits.
Asian Test Symposium 1995: 113-119 |
| 7 | EE | S. Lavabre,
Yves Bertrand,
Michel Renovell,
Christian Landrault:
Test configurations to enhance the testability of sequential circuits.
Asian Test Symposium 1995: 160-168 |
| 6 | EE | Michel Renovell,
P. Huc,
Yves Bertrand:
The concept of resistance interval: a new parametric model for realistic resistive bridging fault.
VTS 1995: 184-189 |
| 1994 |
|---|
| 5 | | Michel Renovell,
P. Huc,
Yves Bertrand:
The Configuration Ratio: A Model for Simulating CMOS Intra-Gate Bridge with Variable Logic Thresholds.
EDCC 1994: 165-177 |
| 4 | | Yves Bertrand,
Jean-François Dufourd:
Algebraic Specification of a 3D-Modeler Based on Hypermaps.
CVGIP: Graphical Model and Image Processing 56(1): 29-60 (1994) |
| 1993 |
|---|
| 3 | | Yves Bertrand,
Frédéric Bancel,
Michel Renovell:
Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits.
ITC 1993: 989-997 |
| 2 | | Yves Bertrand,
Jean-François Dufourd,
Jean Françon,
Pascal Lienhardt:
Algebraic Specification and Development in Geometric Modeling.
TAPSOFT 1993: 75-89 |
| 1 | | Yves Bertrand,
Frédéric Bancel,
Michel Renovell:
A DFT Technique to Improve ATPG Efficiency for Sequential Circuits.
VLSI Design 1993: 51-54 |
