| * | 1991 |
|---|
| 5 | EE | C. Leonard Berman,
Louise Trevillyan:
Global flow optimization in automatic logic design.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 557-564 (1991) |
| 4 | EE | C. Leonard Berman:
Circuit width, register allocation, and ordered binary decision diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 1059-1066 (1991) |
| 1989 |
|---|
| 3 | EE | Ravi Nair,
C. Leonard Berman,
Peter S. Hauge,
Ellen J. Yoffa:
Generation of performance constraints for layout.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(8): 860-874 (1989) |
| 1986 |
|---|
| 2 | | Louise Trevillyan,
William H. Joyner Jr.,
C. Leonard Berman:
Global Flow Analysis in Automatic Logic Design.
IEEE Trans. Computers 35(1): 77-81 (1986) |
| 1981 |
|---|
| 1 | | John A. Darringer,
William H. Joyner Jr.,
C. Leonard Berman,
Louise Trevillyan:
Logic Synthesis Through Local Transformations.
IBM Journal of Research and Development 25(4): 272-280 (1981) |
