Sudarshan Bahukudumbi Vis

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8EESudarshan Bahukudumbi, Krishnendu Chakrabarty: Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs. IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 111-120 (2009)
7EESudarshan Bahukudumbi, Krishnendu Chakrabarty, Richard Kacprowicz: Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs. DATE 2008: 1103-1106
6EESudarshan Bahukudumbi, Krishnendu Chakrabarty: Test-Pattern Ordering for Wafer-Level Test-During-Burn-In. VTS 2008: 193-198
5EEAnuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty: Power-aware SoC test planning for effective utilization of port-scalable testers. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
4EESudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar: AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs. ASP-DAC 2007: 823-828
3EESudarshan Bahukudumbi, Krishnendu Chakrabarty: Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs. VLSI Design 2007: 459-464
2EESudarshan Bahukudumbi, Krishnendu Chakrabarty: Wafer-Level Modular Testing of Core-Based SoCs. IEEE Trans. VLSI Syst. 15(10): 1144-1154 (2007)
1EESudarshan Bahukudumbi, Krishna Bharath: A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores. VLSI Design 2005: 804-807

Coauthor Index

1Krishna Bharath [1]
2Krishnendu Chakrabarty [2] [3] [4] [5] [6] [7] [8]
3Vikram Iyengar [4]
4Richard Kacprowicz [7]
5Sule Ozev [4]
6Anuja Sehgal [5]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)