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R. Iris Bahar Vis

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*2009
54 Fabrizio Lombardi, Sanjukta Bhanja, Yehia Massoud, R. Iris Bahar: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009 ACM 2009
53EECesare Ferri, R. Iris Bahar, Mirko Loghi, Massimo Poncino: Energy-optimal synchronization primitives for single-chip multi-processors. ACM Great Lakes Symposium on VLSI 2009: 141-144
52EERoto Le, Sherief Reda, R. Iris Bahar: High-performance, cost-effective heterogeneous 3D FPGA architectures. ACM Great Lakes Symposium on VLSI 2009: 251-256
51EENuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar: Detecting errors using multi-cycle invariance information. DATE 2009: 791-796
50EERoto Le, Sherief Reda, R. Iris Bahar: High-performance, cost-effective heterogeneous 3D FPGA architectures. FPGA 2009: 286
49EER. Iris Bahar: Introduction to special section: Best of NANOARCH 2008. JETC 5(2): (2009)
2008
48EECesare Ferri, Amber Viescas, Tali Moreshet, R. Iris Bahar, Maurice Herlihy: Energy efficient synchronization techniques for embedded architectures. ACM Great Lakes Symposium on VLSI 2008: 435-440
47EEAndrea Calimera, Enrico Macii, Massimo Poncino, R. Iris Bahar: Temperature-insensitive synthesis using multi-vt libraries. ACM Great Lakes Symposium on VLSI 2008: 5-10
46EEAndrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino: Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. ISLPED 2008: 217-220
45EEDesta Tadesse, R. Iris Bahar, Joel Grodstein: Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. VTS 2008: 339-344
44EER. Iris Bahar, Krishnendu Chakrabarty: Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies. ACM Trans. Design Autom. Electr. Syst. 13(2): (2008)
43EER. Iris Bahar, Krishnendu Chakrabarty: Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies. JETC 4(2): (2008)
42EECesare Ferri, Sherief Reda, R. Iris Bahar: Parametric yield management for 3D ICs: Models and strategies for improvement. JETC 4(4): (2008)
2007
41EEDesta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein: Accurate timing analysis using SAT and pattern-dependent delay models. DATE 2007: 1018-1023
40EEKundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. DATE 2007: 576-581
39EECesare Ferri, Sherief Reda, R. Iris Bahar: Strategies for improving the parametric yield and profits of 3D ICs. ICCAD 2007: 220-226
38EER. Iris Bahar, Dan W. Hammerstrom, Justin E. Harlow III, William H. Joyner Jr., Clifford Lau, Diana Marculescu, Alex Orailoglu, Massoud Pedram: Architectures for Silicon Nanoelectronics and Beyond. IEEE Computer 40(1): 25-33 (2007)
37EEKundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Designing Nanoscale Logic Circuits Based on Markov Random Fields. J. Electronic Testing 23(2-3): 255-266 (2007)
2006
36EEKundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Optimizing noise-immune nanoscale circuits using principles of Markov random fields. ACM Great Lakes Symposium on VLSI 2006: 149-152
35EEVladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss: A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors. DAC 2006: 705-708
34EEKundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Designing MRF based error correcting circuits for memory elements. DATE 2006: 792-793
33EER. Iris Bahar: Trends and Future Directions in Nano Structure Based Computing and Fabrication. ICCD 2006
32EETali Moreshet, R. Iris Bahar, Maurice Herlihy: Energy implications of multiprocessor synchronization. SPAA 2006: 329
31EEKundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. IEEE Micro 26(5): 19-27 (2006)
30EEHui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein: Timing analysis for full-custom circuits using symbolic DC formulations. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1815-1830 (2006)
2005
29EEKundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky: Designing logic circuits for probabilistic computation in the presence of noise. DAC 2005: 485-490
28EETali Moreshet, R. Iris Bahar, Maurice Herlihy: Energy reduction in multiprocessor systems using transactional memory. ISLPED 2005: 331-334
27EER. Iris Bahar, Mehdi Baradaran Tahoori, Sandeep K. Shukla, Fabrizio Lombardi: Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale. IEEE Design & Test of Computers 22(4): 295-297 (2005)
26EER. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein: Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 502-515 (2005)
2004
25EEKundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein: RESTA: a robust and extendable symbolic timing analysis tool. ACM Great Lakes Symposium on VLSI 2004: 407-412
24EENikil Mehta, Brian Singer, R. Iris Bahar, Michael Leuchtenburg, Richard S. Weiss: Fetch Halting on Critical Load Misses. ICCD 2004: 244-249
23EEYu Bai, R. Iris Bahar: Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm. ICCD 2004: 54-57
22EETali Moreshet, R. Iris Bahar: Effects of speculation on performance and issue queue design. IEEE Trans. VLSI Syst. 12(10): 1123-1126 (2004)
21EEYu Bai, R. Iris Bahar: A low-power in-order/out-of-order issue queue. TACO 1(2): 152-179 (2004)
2003
20EETali Moreshet, R. Iris Bahar: Power-aware issue queue design for speculative instructions. DAC 2003: 634-637
19EER. Iris Bahar, Joseph L. Mundy, Jie Chen: A Probabilistic-Based Design Methodology for Nanoscale Computation. ICCAD 2003: 480-486
18EEHui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein: Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current. ICCD 2003: 70-75
17EEYu Bai, R. Iris Bahar: A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors. ISVLSI 2003: 139-148
16EEEric Chi, A. Michael Salem, R. Iris Bahar, Richard S. Weiss: Combining Software and Hardware Monitoring for Improved Power and Performance Tuning. Interaction between Compilers and Computer Architectures 2003: 57-64
2002
15 Hui-Yuan Song, R. Iris Bahar, Joel Grodstein: Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations. IWLS 2002: 203-208
2001
14EER. Iris Bahar, Srilatha Manne: Power and energy reduction via pipeline balancing. ISCA 2001: 218-229
2000
13EERoberto Maro, Yu Bai, R. Iris Bahar: Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors. PACS 2000: 97-111
12EER. Iris Bahar, Ernest T. Lampe, Enrico Macii: Power optimization of technology-dependent circuits based on symbolic computation of logic implications. ACM Trans. Design Autom. Electr. Syst. 5(3): 267-293 (2000)
1999
11EEBrian R. Fisk, R. Iris Bahar: The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency. ICCD 1999: 538-545
1998
10EER. Iris Bahar, Gianluca Albera, Srilatha Manne: Power and performance tradeoffs using various caching strategies. ISLPED 1998: 64-69
1997
9 R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi: Algebraic Decision Diagrams and Their Applications. Formal Methods in System Design 10(2/3): 171-206 (1997)
8EER. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi: Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1101-1115 (1997)
1996
7EER. Iris Bahar, M. Burns, Gary D. Hachtel, Enrico Macii, H. Shin, Fabio Somenzi: Symbolic computation of logic implications for technology-dependent low-power synthesis. ISLPED 1996: 163-168
1995
6EESrilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino: Computing the Maximum Power Cycles of a Sequential Circuit. DAC 1995: 23-28
5EER. Iris Bahar, Fabio Somenzi: Boolean techniques for low power driven re-synthesis. ICCAD 1995: 428-432
4EEAbelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi: CMOS dynamic power estimation based on collapsible current source transistor modeling. ISLPD 1995: 111-116
1994
3 R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi: Timing Analysis of Combinational Circuits using ADD's. EDAC-ETC-EUROASIC 1994: 625-629
2EER. Iris Bahar, Gary D. Hachtel, Enrico Macii, Fabio Somenzi: A symbolic method to reduce power consumption of circuits containing false paths. ICCAD 1994: 368-371
1993
1EER. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi: Algebraic decision diagrams and their applications. ICCAD 1993: 188-191

Coauthor Index

1Gianluca Albera [10]
2Nuno Alves [51]
3Yu Bai [13] [17] [21] [23]
4Sanjukta Bhanja [54]
5S. Bohidar [18]
6M. Burns [7]
7Andrea Calimera [46] [47]
8Krishnendu Chakrabarty [43] [44]
9Jie Chen [19]
10Eric Chi [16]
11Hyunwoo Cho [3] [8]
12Jennifer Dworak [35] [51]
13Peter Feldmann [4]
14Cesare Ferri [39] [42] [48] [53]
15Brian R. Fisk [11]
16Erica A. Frohm [1] [9]
17Charles M. Gaona [1] [9]
18Joel Grodstein [15] [18] [25] [26] [30] [41] [45]
19Gary D. Hachtel [1] [2] [3] [4] [6] [7] [8] [9]
20Dan W. Hammerstrom [38]
21Justin E. Harlow III [38]
22Maurice Herlihy [28] [32] [48]
23William H. Joyner Jr. [38]
24Ernest T. Lampe [12]
25Clifford Lau [38]
26Roto Le [50] [52]
27E. Lenge [41]
28Michael Leuchtenburg [24]
29Mirko Loghi [53]
30Fabrizio Lombardi [27] [54]
31Enrico Macii [1] [2] [3] [6] [7] [8] [9] [12] [46] [47]
32Srilatha Manne [4] [6] [10] [14]
33Diana Marculescu [38]
34Roberto Maro [13]
35Yehia Massoud [54]
36Nikil Mehta [24]
37Tali Moreshet [20] [22] [28] [32] [48]
38Joseph L. Mundy [19] [29] [31] [34] [36] [37] [40]
39Kundan Nepal [25] [26] [29] [30] [31] [34] [36] [37] [40] [51]
40Alex Orailoglu [38]
41Abelardo Pardo [1] [4] [6] [9]
42William R. Patterson [29] [31] [34] [36] [37] [40]
43Massoud Pedram [38]
44Massimo Poncino [6] [46] [47] [53]
45Sherief Reda [39] [42] [50] [52]
46A. Michael Salem [16]
47D. Sheffield [41]
48H. Shin [7]
49Sandeep K. Shukla [27]
50Brian Singer [24]
51Fabio Somenzi [1] [2] [3] [4] [5] [6] [7] [8] [9]
52Hui-Yuan Song [15] [18] [25] [26] [30]
53Vladimir Stojanovic [35]
54Desta Tadesse [41] [45]
55Mehdi Baradaran Tahoori [27]
56Amber Viescas [48]
57Richard Weiss [35]
58Richard S. Weiss [16] [24]
59Alexander Zaslavsky [29] [31] [34] [36] [37] [40]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)