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Gregg Baeckler Vis

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*2006
4EESean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan: Efficient SAT-based Boolean matching for FPGA technology mapping. DAC 2006: 466-471
3EEMichael Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo: A methodology for FPGA to structured-ASIC synthesis and verification. DATE Designers' Forum 2006: 64-69
2005
2EEDavid M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose: The Stratix II logic and routing architecture. FPGA 2005: 14-20
2004
1EEMichael Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini: Improving FPGA Performance and Area Using an Adaptive Logic Module. FPL 2004: 135-144

Coauthor Index

1Elias Ahmed [2]
2Vaughn Betz [2]
3Mark Bourgeault [1] [2]
4David Cashman [2]
5Sammy Cheung [3]
6Kar Keng Chua [3]
7Richard Cliff [2]
8David R. Galloway [2]
9Michael Hutton (Michael D. Hutton, Mike Hutton) [1] [2] [3]
10Sinan Kaptanoglu [1]
11Henry Kim [1]
12Christopher Lane [2]
13Andy Lee [1] [2]
14Paul Leventis [2]
15David M. Lewis [1] [2]
16Sandy Marquardt [2]
17Cameron McClintock [2]
18Ketan Padalia [1] [2]
19Bruce Pedersen [1] [2]
20Hee Kong Phoo [3]
21Giles Powell [2]
22Boris Ratchev [1] [2]
23Srinivas Reddy [2]
24Jonathan Rose [2]
25Sean Safarpour [4]
26Rahul Saini [1]
27Jay Schleicher [1] [2] [3]
28Kevin Stevens [2]
29Andreas G. Veneris [4]
30Richard Yuan [1] [2] [3] [4]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)