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Dariusz Badura Vis

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*1997
3EEDariusz Badura, Andrzej Hlawiczka: Low Cost Bist for Edac Circuits. Asian Test Symposium 1997: 410-415
1989
2 Dariusz Badura: Efficiency of Self-Test Path as a Test Pattern Generator and Test Response Compactor. Fehlertolerierende Rechensysteme 1989: 368-378
1987
1 Andrzej Hlawiczka, Dariusz Badura: Universal Test Controller Chip for Board Self Test. Fehlertolerierende Rechensysteme 1987: 165-175

Coauthor Index

1Andrzej Hlawiczka [1] [3]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)