dblp.uni-trier.dewww.uni-trier.de

Hafiz Md. Hasan Babu Vis

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeerX - CSB - MetaPress - Google - Bing - Yahoo

*2008
17EEMuhammad Ibrahim, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu: Minimization of CTS of k-CNOT Circuits for SSF and MSF Model. DFT 2008: 290-298
16EEAshis Kumer Biswas, Md. Mahmudul Hasan, Moshaddek Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu: A Novel Approach to Design BCD Adder and Carry Skip BCD Adder. VLSI Design 2008: 566-571
2006
15 Amin Ahsan Ali, Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury: Realization of Digital Fuzzy Operations Using Multi-Valued Fredkin Gates. CDES 2006: 101-106
14EEAhsan Raja Chowdhury, Rumana Nazmul, Hafiz Md. Hasan Babu: A New Approach to Synthesize Multiple-Output Functions Using Reversible Programmable Logic Array. VLSI Design 2006: 311-316
13EEHafiz Md. Hasan Babu, Ahsan Raja Chowdhury: Design of a compact reversible binary coded decimal adder circuit. Journal of Systems Architecture 52(5): 272-282 (2006)
2005
12EEMd. Sumon Shahriar, A. R. Mustafa, Chowdhury Farhan Ahmed, Abu Ahmed Ferdaus, A. N. M. Zaheduzzaman, Shahed Anwar, Hafiz Md. Hasan Babu: An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions Using LUT and Realization Using Current Mode CMOS. DSD 2005: 122-126
11EEHafiz Md. Hasan Babu, Ahsan Raja Chowdhury: Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder. VLSI Design 2005: 255-260
2004
10EEHafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Mazder Rahman, Md. Rafiqul Islam: Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic. DSD 2004: 603-606
9 Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Rumana Nazmul, Md. Anwarul Haque, Ahsan Raja Chowdhury: A heuristic approach to synthesize Boolean functions using TANT network. ISCAS (2) 2004: 373-376
8EEHafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Rafiqul Islam, Md. Mazder Rahman: On the Minimization of Multiple-Valued Input Binary-Valued Output Functions. ISMVL 2004: 321-326
7EEHafiz Md. Hasan Babu, Md. Rafiqul Islam, Syed Mostahed Ali Chowdhury, Ahsan Raja Chowdhury: Synthesis of Full-Adder Circuit Using Reversible Logic. VLSI Design 2004: 757-760
2003
6EEMd. Rafiqul Islam, Hafiz Md. Hasan Babu, Mohammad Abdur Rahim Mustafa, Md. Sumon Shahriar: A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor Logic. Asian Test Symposium 2003: 90-95
5EEHafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury: Reversible Logic Synthesis for Minimization of Full-Adder Circuit. DSD 2003: 50-54
4EEHafiz Md. Hasan Babu, Md. Rafiqul Islam, Amin Ahsan Ali, Mohammad Musa Salehin Akon: A Technique for Logic Design of Voltage-Mode Pass Transistor Based Multi-Valued Multiple-Output Logic Circuits. ISMVL 2003: 111-116
2000
3EEHafiz Md. Hasan Babu, Tsutomu Sasao: Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams. ISMVL 2000: 147-152
1999
2EEHafiz Md. Hasan Babu, Tsutomu Sasao: Shared Multiple-Valued Decision Diagrams for Multiple-Output Functions. ISMVL 1999: 166-172
1998
1EEHafiz Md. Hasan Babu, Tsutomu Sasao: Design of Multiple-Output Networks using Time Domain Multiplexing and Shared Multi-Terminal Multiple-Valued Decision Diagrams. ISMVL 1998: 45-51

Coauthor Index

1Chowdhury Farhan Ahmed [12]
2Mohammad Musa Salehin Akon [4]
3Amin Ahsan Ali [4] [15]
4Shahed Anwar [12]
5Ashis Kumer Biswas [16]
6Ahsan Raja Chowdhury [5] [7] [9] [11] [13] [14] [15] [16] [17]
7Syed Mostahed Ali Chowdhury [5] [7]
8Abu Ahmed Ferdaus [12]
9Md. Anwarul Haque [9]
10Md. Mahmudul Hasan [16]
11Moshaddek Hasan [16]
12Muhammad Ibrahim [17]
13Md. Rafiqul Islam [4] [5] [6] [7] [8] [9] [10]
14A. R. Mustafa [12]
15Mohammad Abdur Rahim Mustafa [6]
16Rumana Nazmul [9] [14]
17Md. Mazder Rahman [8] [10]
18Tsutomu Sasao [1] [2] [3]
19Md. Sumon Shahriar [6] [12]
20Moinul Islam Zaber [8] [10]
21A. N. M. Zaheduzzaman [12]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)