Markus Bühler Vis

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4EEPhilipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl: Considering possible opens in non-tree topology wire delay calculation. ACM Great Lakes Symposium on VLSI 2008: 17-22
3EEMarkus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, R. Sommer, Michael Pronath, Andreas Ripp: DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. DATE 2006: 387-392
2EEJeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Muller, Sven Peyer, Christian Schulte: Yield Improvement by Local Wiring Redundancy. ISQED 2006: 473-478
1EEMarkus Bühler, Matthias Papesch, K. Kapp, Utz G. Baitinger: Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach. DATE 1999: 459-

Coauthor Index

1Utz G. Baitinger [1]
2Erich Barke [4]
3Jeanne Bickford [2] [3]
4Jason Hibbeler [2] [3]
5K. Kapp [1]
6Jürgen Koehl [2] [3] [4]
7Dirk Muller [2]
8Markus Olbrich [4]
9Philipp V. Panitz [4]
10Matthias Papesch [1]
11Sven Peyer [2]
12Michael Pronath [3]
13Andreas Ripp [3]
14Ulf Schlichtmann [3]
15Christian Schulte [2]
16R. Sommer [3]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)