Daniel Auvergne Vis

*	2007
35	EE	Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Low Power Oriented CMOS Circuit Optimization Protocol CoRR abs/0710.4760: (2007)
	2006
34	EE	B. Lasbouygues, S. Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Logical effort model extension to propagation delay representation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1677-1684 (2006)
	2005
33	EE	Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Low Power Oriented CMOS Circuit Optimization Protocol. DATE 2005: 640-645
	2004
32		Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Delay bound based CMOS gate sizing technique. ISCAS (5) 2004: 189-192
31	EE	Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Performance Metric Based Optimization Protocol. PATMOS 2004: 100-109
30	EE	B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Temperature Dependence in Low Power CMOS UDSM Process. PATMOS 2004: 110-118
29	EE	A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne: Design Optimization with Automated Cell Generation. PATMOS 2004: 722-731
28	EE	B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Physical Extension of the Logical Effort Model. PATMOS 2004: 838-848
	2003
27	EE	Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Metric Definition for Circuit Speed Optimization. PATMOS 2003: 451-460
26	EE	Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne: CMOS Gate Sizing under Delay Constraint. PATMOS 2003: 60-69
25	EE	Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne: Design Techniques for EEPROMs Embedded in Portable Systems on Chips. IEEE Design & Test of Computers 20(1): 68-75 (2003)
	2002
24	EE	Philippe Maurine, Xavier Michel, Nadine Azémard, Daniel Auvergne: Gate speed improvement at minimal power dissipation. APCCAS (2) 2002: 325-330
23	EE	W. Rahajandraibe, Christian Dufaza, Daniel Auvergne, B. Cialdella, B. Majoux, V. Chowdhury: Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications. DATE 2002: 316-321
22	EE	A. Landrault, L. Pellier, A. Richard, C. Jay, Michel Robert, Daniel Auvergne: Transistor Level Synthesis Dedicated to Fast I.P. Prototyping. PATMOS 2002: 156-166
21	EE	Philippe Maurine, Nadine Azémard, Daniel Auvergne: Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS 2002: 247-257
20	EE	Fabrice Picot, Philippe Coll, Daniel Auvergne: Crosstalk Measurement Technique for CMOS ICs. PATMOS 2002: 65-70
19	EE	Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne: Transition time modeling in deep submicron CMOS. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1352-1363 (2002)
	2001
18	EE	Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne: Output transition time modeling of CMOS structures. ISCAS (5) 2001: 363-366
17	EE	Nadine Azémard, M. Aline, Daniel Auvergne: Delay bound determination for timing closure satisfaction. ISCAS (5) 2001: 375-378
16		Philippe Maurine, Nadine Azémard, Daniel Auvergne: Gate Sizing for Low Power Design. VLSI-SOC 2001: 301-312
15		Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne: Feasible Delay Bound Definition. VLSI-SOC 2001: 325-335
14	EE	Nadine Azémard, Daniel Auvergne: POPS: A tool for delay/power performance optimization. Journal of Systems Architecture 47(3-4): 375-382 (2001)
	2000
13	EE	Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne: Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions. MTDT 2000: 39-46
12	EE	Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne: Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design. PATMOS 2000: 129-138
11	EE	Mustapha Rezzoug, Philippe Maurine, Daniel Auvergne: Second Generation Delay Model for Submicron CMOS Process. PATMOS 2000: 159-167
	1999
10		Augusto Gallegos, Philippe Silvestre, Michel Robert, Daniel Auvergne: RF Interface Design Using Mixed-Mode Methodology. VLSI 1999: 326-333
9		Fernando Moraes, Michel Robert, Daniel Auvergne: A Virtual CMOS Library Approach for East Layout Synthesis. VLSI 1999: 415-426
	1998
8	EE	Jean Michel Daga, E. Ottaviano, Daniel Auvergne: Temperature Effect on Delay for Low Voltage Applications. DATE 1998: 680-685
7	EE	S. Turgis, Daniel Auvergne: A novel macromodel for power estimation in CMOS structures. IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1090-1098 (1998)
	1997
6	EE	S. Turgis, Jean Michel Daga, J. M. Portal, Daniel Auvergne: Internal power modelling and minimization in CMOS inverters. ED&TC 1997: 603-608
	1995
5	EE	Jean Michel Daga, Michel Robert, Daniel Auvergne: Delay modelling improvement for low voltage applications. EURO-DAC 1995: 216-221
4	EE	S. Turgis, Nadine Azémard, Daniel Auvergne: Explicit evaluation of short circuit power dissipation for CMOS logic structures. ISLPD 1995: 129-134
	1994
3		Michel Robert, Lionel Torres, Fernando Moraes, Daniel Auvergne: Influence of Locig Block Layout Architecture on FPGA Performance. FPL 1994: 34-44
	1993
2	EE	Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne: Post-layout timing simulation of CMOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1170-1177 (1993)
	1990
1	EE	Denis Deschacht, P. Pinede, Michel Robert, Daniel Auvergne: Path runner: an accurate and fast timing analyser. EURO-DAC 1990: 529-533

Coauthor Index

1	M. Aline	[15] [17]
2	Nadine Azémard (Nadine Azémard-Crestani)	[2] [4] [14] [15] [16] [17] [19] [21] [24] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35]
3	V. Chowdhury	[23]
4	B. Cialdella	[23]
5	Philippe Coll	[20]
6	Jean Michel Daga	[5] [6] [8] [13] [25]
7	Denis Deschacht	[1] [2]
8	Christian Dufaza	[23]
9	S. Engels	[34]
10	Augusto Gallegos	[10]
11	Jeanine Guichaoua	[13] [25]
12	C. Jay	[22]
13	A. Landrault	[22] [29]
14	B. Lasbouygues	[28] [30] [34]
15	B. Majoux	[23]
16	Philippe Maurine	[11] [12] [15] [16] [18] [19] [21] [24] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35]
17	Giuseppe Medulla	[13] [25]
18	Marc Merandat	[13] [25]
19	Xavier Michel	[24] [26] [27] [31] [32] [33] [35]
20	Fernando Gehm Moraes (Fernando Moraes)	[3] [9]
21	E. Ottaviano	[8]
22	Caroline Papaix	[13] [25]
23	L. Pellier	[22]
24	Fabrice Picot	[20]
25	P. Pinede	[1]
26	J. M. Portal	[6]
27	W. Rahajandraibe	[23]
28	Mustapha Rezzoug	[11] [12] [18] [19]
29	Stephane Ricard	[13] [25]
30	A. Richard	[22]
31	Michel Robert	[1] [2] [3] [5] [9] [10] [22] [29]
32	Philippe Silvestre	[10]
33	Lionel Torres	[3]
34	S. Turgis	[4] [6] [7]
35	Alexandre Verle	[26] [27] [31] [32] [33] [35]
36	Robin Wilson	[28] [30] [34]

Colors in the list of coauthors