| |
| 1995 | ||
|---|---|---|
| 4 | EE | Siamak Arya, Howard Sachs, Sreeram Duvvuru: An architecture for high instruction level parallelism. HICSS (1) 1995: 153-162 |
| 3 | EE | Sreeram Duvvuru, Siamak Arya: Evaluation of a branch target address cache. HICSS (1) 1995: 173-180 |
| 1988 | ||
| 2 | EE | Siamak Arya, Blaine Gaither: Parallel algorithm development workbench. SC 1988: 11-17 |
| 1985 | ||
| 1 | Siamak Arya: An Optimal Instruction-Scheduling Model for a Class of Vector Processors. IEEE Trans. Computers 34(11): 981-995 (1985) | |
| 1 | Sreeram Duvvuru | [3] [4] |
| 2 | Blaine Gaither | [2] |
| 3 | Howard Sachs | [4] |