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Hideharu Amano Vis

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*2009
157EETomoya Ishimori, Hideki Yamada, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Kiyoshi Oguri: Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator. ARC 2009: 368-373
156EELei Zhao, Hui Xu, Naomi Seki, Saito Yoshiki, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano: Cache Controller Design on Ultra Low Leakage Embedded Processors. ARCS 2009: 171-182
155EEHiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga: Prediction router: Yet another low latency on-chip router architecture. HPCA 2009: 367-378
154EEMichihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano: An on/off link activation method for low-power ethernet in PC clusters. IPDPS 2009: 1-11
153EEVu Manh Tuan, Naohiro Katsura, Hiroki Matsutani, Hideharu Amano: Evaluation of a multicore reconfigurable architecture with variable core sizes. IPDPS 2009: 1-8
152 Jose Miguel Montanana Aliaga, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano: An On/Off Link Activation Method for Power Regulation in InfiniBand. PDPTA 2009: 289-295
151EEKimiyoshi Usami, Toshiaki Shirai, Tasunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura: Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design 2009: 381-386
150EEHiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano: Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IEEE Trans. Parallel Distrib. Syst. 20(8): 1126-1141 (2009)
149EEDaihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Transactions 92-D(4): 575-583 (2009)
148EEHideharu Amano, Tadao Nakamura: Guest Editors' Introduction: ICFPT 2007. TRETS 2(2): (2009)
2008
147EEVu Manh Tuan, Hideharu Amano: A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor. ARC 2008: 171-182
146EEHiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang: Run-time power gating of on-chip routers using look-ahead routing. ASP-DAC 2008: 55-60
145 Vu Manh Tuan, Hideharu Amano: A Method for Capturing State Data on Dynamically Reconfigurable Processors. ERSA 2008: 208-214
144 Masaru Kato, Yohei Hasegawa, Hideharu Amano: Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs. ERSA 2008: 215-221
143EEToru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano: Instruction buffer mode for multi-context Dynamically Reconfigurable Processors. FPL 2008: 215-220
142EEDaihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi: A link removal methodology for Networks-on-Chip on reconfigurable systems. FPL 2008: 269-274
141EETakashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsusmi, Vasutan Tunbunheng, Hideharu Amano: Power reduction techniques for Dynamically Reconfigurable Processor Arrays. FPL 2008: 305-310
140EEMasato Yoshimi, Yuri Nishikawa, Yasunori Osana, Akira Funahashi, Yuichiro Shibata, Hideki Yamada, Noriko Hiroi, Hiroaki Kitano, Hideharu Amano: Practical implementation of a network-based stochastic biochemical simulation system on an FPGA. FPL 2008: 663-666
139EENaomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura: A fine-grain dynamic sleep control scheme in MIPS R3000. ICCD 2008: 612-617
138EEHiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano: Three-Dimensional Layout of On-Chip Tree-Based Networks. ISPAN 2008: 281-288
137EEMichihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston: A Lightweight Fault-Tolerant Mechanism for Network-on-Chip. NOCS 2008: 13-22
136EEHiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano: Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. NOCS 2008: 23-32
135EEVasutan Tunbunheng, Hideharu Amano: A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor Arrays. IEICE Transactions 91-D(11): 2655-2665 (2008)
134EEVu Manh Tuan, Hideharu Amano: A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors. IEICE Transactions 91-D(12): 2793-2803 (2008)
133EEVu Manh Tuan, Hideharu Amano: A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors. IEICE Transactions 91-D(9): 2312-2322 (2008)
2007
132EETakamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka: Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGA. CIT 2007: 567-572
131 Vu Manh Tuan, Yohei Hasegawa, Hideharu Amano: Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor. ERSA 2007: 203-206
130EEMasato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hideki Yamada, Hiroaki Kitano, Hideharu Amano: FPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction Method. FPL 2007: 254-259
129EEDaihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. FPL 2007: 383-388
128EETakamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka: A High Speed License Plate Recognition System on an FPGA. FPL 2007: 554-557
127EEYohei Hasegawa, Hideharu Amano: Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays. FPL 2007: 796-799
126EEHideki Yamada, Naoki Iwanaga, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri: A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator. FPL 2007: 808-811
125EEHiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. ICPP 2007: 75
124EEYuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano: Performance Improvement Methodology for ClearSpeed's CSX600. ICPP 2007: 77
123EEHiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IPDPS 2007: 1-10
122 Atushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo: Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot. PDPTA 2007: 787-793
121 Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano: Performance evaluation on low-latency communication mechanism of DIMMnet-2. Parallel and Distributed Computing and Networks 2007: 57-62
120EEAkiya Jouraku, Michihiro Koibuchi, Hideharu Amano: An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks. IEEE Trans. Parallel Distrib. Syst. 18(3): 320-333 (2007)
119EEKonosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hiroaki Nishi, Junji Yamamoto, Noboru Tanabe, Tomohiro Kudoh, Hideharu Amano: Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs. IEEE Trans. Parallel Distrib. Syst. 18(9): 1282-1295 (2007)
118EEDaihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Transactions 90-D(12): 1914-1922 (2007)
117EEVasutan Tunbunheng, Masayasu Suzuki, Hideharu Amano: Data Multicasting Procedure for Increasing Configuration Speed of Coarse Grain Reconfigurable Devices. IEICE Transactions 90-D(2): 473-481 (2007)
2006
116EEVu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano: Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor. ARC 2006: 115-121
115 Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano: A Parametric Study of Scalable Interconnects on FPGAs. ERSA 2006: 130-135
114EEHideharu Amano, Yohei Hasegawa, Shohei Abe, K. Ishikawa, Shunsuke Tsutsumi, Shunsuke Kurotaki, Takuro Nakamura, Takashi Nishimura: A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors. FPL 2006: 1-6
113EEMasato Yoshimi, Yasunori Osana, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano: An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems. FPL 2006: 1-6
112EEYasunori Osana, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano: Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSip. FPL 2006: 1-6
111EETomohiro Otsuka, Michihiro Koibuchi, Tomohiro Kudoh, Hideharu Amano: Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet. ICPP 2006: 479-486
110EEMasayasu Suzuki, Yohei Hasegawa, Vu Manh Tuan, Shohei Abe, Hideharu Amano: A cost-effective context memory structure for dynamically reconfigurable processors. IPDPS 2006
109EEYohei Hasegawa, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan, Naohiro Katsura, Takuro Nakamura, Takashi Nishimura, Hideharu Amano: Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. IPDPS 2006
108 Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. ISCA PDCS 2006: 24-31
107EEHiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. ISPA 2006: 207-218
106EEMichihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano: A Simple Data Transfer Technique Using Local Address for Networks-on-Chips. IEEE Trans. Parallel Distrib. Syst. 17(12): 1425-1437 (2006)
105EEHideharu Amano: A Survey on Dynamically Reconfigurable Processors. IEICE Transactions 89-B(12): 3179-3187 (2006)
2005
104 Katsuaki Deguchi, Shohei Abe, Masayasu Suzuki, Kenichiro Anjo, Toru Awashima, Hideharu Amano: Implementing core tasks of JPEG2000 Encoder on the Dynamically Reconfigurable Processor. ARCS Workshops 2005: 12-18
103EEHideharu Amano, Shohei Abe, Yohei Hasegawa, Katsuaki Deguchi, Masayasu Suzuki: Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor. FCCM 2005: 315-316
102EEYohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano: Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation. FPGA 2005: 265
101 Hideharu Amano, Shohei Abe, Katsuaki Deguchi, Yohei Hasegawa: An I/O mechanism on a Dynamically Reconfigurable Processor - Which should be moved: Data or Configuration? FPL 2005: 347-352
100 Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano: A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGA. FPL 2005: 574-577
99 Naoki Iwanaga, Yuichiro Shibata, Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri: Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA. FPL 2005: 666-669
98 Vasutan Tunbunheng, Masayasu Suzuki, Hideharu Amano: RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable Devices. FPT 2005: 129-136
97 Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima: An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor. FPT 2005: 163-170
96 Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano: The Design of Scalable Stochastic Biochemical Simulator on FPGA. FPT 2005: 339-340
95EETomohiro Otsuka, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: VLAN-Based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus. ICPP 2005: 567-576
94EEHiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano: Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. ICPP Workshops 2005: 273-280
93EEYasunori Osana, Tomonori Fukushima, Masato Yoshimi, Yow Iwaoka, Yuichiro Shibata, Hiroaki Kitano, Akira Funahashi, Noriko Hiroi, Hideharu Amano: An FPGA-Based, Multi-model Simulation Method for Biochemical Systems. IPDPS 2005
92EEAkira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo: Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board. PDCAT 2005: 778-780
91 Toshihiro Hanawa, Toshiya Minai, Yasuki Tanabe, Hideharu Amano: Implementation of ISIS-SimpleScalar. PDPTA 2005: 117-123
90 Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips. PDPTA 2005: 1343-1349
89 Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo: A Packet Forwarding Layer for DIMMnet and its Hardware Implementation. PDPTA 2005: 461-467
88EEMichihiro Koibuchi, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano: Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster. IEEE Trans. Parallel Distrib. Syst. 16(8): 747-759 (2005)
87EEMichihiro Koibuchi, Akiya Jouraku, Hideharu Amano: MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing. IEICE Transactions 88-D(1): 109-118 (2005)
86EEMichihiro Koibuchi, Akiya Jouraku, Hideharu Amano: Path selection algorithm: the strategy for designing deterministic routing from alternative paths. Parallel Computing 31(1): 117-130 (2005)
85EETakashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Yasuki Tanabe, Toshihiro Hanawa, Hideharu Amano: The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism). Parallel Computing 31(3-4): 352-370 (2005)
2004
84EEYasunori Osana, Tomonori Fukushima, Hideharu Amano: ReCSiP: a reconfigurable cell simulation platform: accelerating biological applications with FPGA. ASP-DAC 2004: 731-733
83EEMasahiko Kawamura, Hideharu Amano: Future reconfigurable computing system. ASP-DAC 2004: 798
82EEYutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura: Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array. EUC 2004: 301-311
81EENoriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima: Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. FCCM 2004: 328-329
80EEMasato Yoshimi, Yasunori Osana, Tomonori Fukushima, Hideharu Amano: Stochastic Simulation for Biochemical Reactions on FPGA. FPL 2004: 105-114
79EEHideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu Suzuki: Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases. FPL 2004: 464-473
78EEKenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips. IPDPS 2004
77 Masato Sumiyoshi, Takashi Midorikawa, Yasuki Tanabe, Hideharu Amano: Design and Evaluation of a Switch Architecture for Multistage Interconnection Network with Temporary Directory. ISCA PDCS 2004: 296-301
76EENoboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano: A New Memory Module for Memory Intensive Applications. PARELEC 2004: 123-128
2003
75 Alexander V. Veidenbaum, Kazuki Joe, Hideharu Amano, Hideo Aiso: High Performance Computing, 5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings Springer 2003
74 Tomohiro Otsuka, Konosuke Watanabe, Junichiro Tsuchiya, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Hideharu Amano: Performance Evaluation of a Prototype of RHiNET-2: A Network-based Distributed Parallel Computing System. Applied Informatics 2003: 738-743
73EEKonosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hideharu Amano, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh: Performance Evaluation of RHiNET-2/NI: A Network Interface for Distributed Parallel Computing Systems. CCGRID 2003: 318-325
72EEMichihiro Koibuchi, Konosuke Watanabe, Kenichi Kono, Akiya Jouraku, Hideharu Amano: Performance Evaluation of Routing Algorithms in RHiNET-2 Cluster. CLUSTER 2003: 395-
71EEHideharu Amano, Akiya Jouraku, Kenichiro Anjo: A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device. FPL 2003: 161-170
70EEToshiro Kitaoka, Hideharu Amano, Kenichiro Anjo: Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device. FPL 2003: 171-180
69EEYasunori Osana, Tomonori Fukushima, Hideharu Amano: Implementation of ReCSiP: A ReConfigurable Cell SImulation Platform. FPL 2003: 766-775
68EEMichihiro Koibuchi, Akiya Jouraku, Konosuke Watanabe, Hideharu Amano: Descending Layers Routing: A Deadlock-Free Deterministic Routing using Virtual Channels in System Area Networks with Irregular Topologies. ICPP 2003: 527-
67 Yasuki Tanabe, Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Toshihiro Hanawa, Hideharu Amano: Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism. PDPTA 2003: 1148-1154
66 Noriaki Suzuki, Hideharu Amano: Performance Evaluation of Instruction Set Architecture of MBP-Light: A Distributed Memory Controller for a Large Scale Multiprocessor. PDPTA 2003: 1155-1164
2002
65EENaoto Kaneko, Hideharu Amano: A General Hardware Design Model for Multicontext FPGAs. FPL 2002: 1037-1047
64EENaoyuki Izu, Tomonori Yokoyama, Junichiro Tsuchiya, Konosuke Watanabe, Hideharu Amano: RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing. FPL 2002: 1118-1121
63EEAkiya Jouraku, Michihiro Koibuchi, Hideharu Amano, Akira Funahashi: Routing Algorithms Based on 2D Turn Model for Irregular Networks. ISPAN 2002: 289-294
62EENoboru Tanabe, Yoshihiro Hamada, Hironori Nakajo, Hideki Imashiro, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano: Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot. PARELEC 2002: 9-14
61 Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: The Impact of Path Selection Algorithm of Adaptive Routing for Implementing Deterministic Routing. PDPTA 2002: 1431-1437
60 Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano: Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot. Cluster Computing 5(1): 7-17 (2002)
2001
59EEDaisuke Kawakami, Yuichiro Shibata, Hideharu Amano: A prototype chip of multicontext FPGA with DRAM for virtual hardware. ASP-DAC 2001: 17-18
58 Akira Funahashi, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: The impact of output selection function on adaptive routing. Computers and Their Applications 2001: 241-246
57EEMichihiro Koibuchi, Akira Funahashi, Akiya Jouraku, Hideharu Amano: L-Turn Routing: An Adaptive Routing in Irregular Networks. ICPP 2001: 383-392
56 Michihiro Koibuchi, Akiya Jouraku, Akira Funahashi, Hideharu Amano: MMLRU Selection Function: An Output Selection Function on Adaptive Routing. ISCA PDCS 2001: 1-6
55EEYulu Yang, Akira Funahashi, Akiya Jouraku, Hiroaki Nishi, Hideharu Amano, Toshinori Sueyoshi: Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers. IEEE Trans. Parallel Distrib. Syst. 12(7): 701-715 (2001)
54EEHiroaki Nishi, Koji Tasho, Tomohiro Kudoh, Hideharu Amano: A network switch for supporting high-performance parallel processing by computers distributed in local areas. Systems and Computers in Japan 32(14): 24-33 (2001)
2000
53EETakahiro Kawaguchi, Takayuki Suzuki, Hideharu Amano: A floating point arithmetic unit for a static scheduling and compiler oriented multiprocessor system. ASP-DAC 2000: 31-32
52EENoboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano: MEMOnet : Network interface plugged into a memory slot. CLUSTER 2000: 17-16
51EEOu Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano: A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. FCCM 2000: 291-294
50EEYuichiro Shibata, Masaki Uno, Hideharu Amano, K. Furuta, Taro Fujii, Masato Motomura: A Virtual Hardware System on a Dynamically Reconfigurable Logic Device. FCCM 2000: 295-296
49EEOu Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano: A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. FPL 2000: 475-484
48EEHideharu Amano, Yuichiro Shibata, Masaki Uno: Reconfigurable Systems: New Activities in Asia. FPL 2000: 585-594
47EEAtsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hideharu Amano: Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware. FPL 2000: 685-694
46EEHiroaki Nishi, Koji Tasho, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano: A Local Area System Network RHinet-1: A Network for High Performance Parallel Computing. HPDC 2000: 296-297
45EENoboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano: On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism. ISPAN 2000: 186-194
44 Hironori Nakajo, M. Ishii, T. Kudo, Hideharu Amano: Coherence Protocol for Home Proxy Cache on RHiNET. PDPTA 2000
43 Shinji Nishimura, K. Harasawa, N. Matsudaira, S. Akutsu, Tomohiro Kudoh, Hiroaki Nishi, Hideharu Amano: RHiNET-2/SW a Hight-throughput, Compact Network-switch Using 8.8-Gbit/s Optical Interconnection. New Generation Comput. 18(2): 187- (2000)
1999
42 Masaki Wakabayashi, Keisuke Inoue, Hideharu Amano: ISIS: Multiprocessor Simulator Library. Applied Informatics 1999: 198-200
41 Xiaoshe Dong, Tomohiro Kudoh, Hideharu Amano: A Routing Algorithm for DS-WDM Ring. Applied Informatics 1999: 562-565
40 Takahiro Kawaguchi, Takashi Fujiwara, Katsuto Sakamoto, Keisuke Iwai, Hideharu Amano: Floating Point Arithmetic Unit for the Custom Processor Maple. Applied Informatics 1999: 578-580
39EEAtsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hidenori Miyazaki, Koichi Higure, Xiao-ping Ling, Hideharu Amano: Implementation and Evaluation of the Compiler for WASMII, a Virtual Hardware System. ICPP Workshops 1999: 346-351
38EEYuichiro Shibata, Xiao-ping Ling, Hideharu Amano: Internal Parallelization of Data-Driven Virtual Hardware. ICPP Workshops 1999: 366-
37EEQin Fan, Yulu Yang, Akira Funahashi, Hideharu Amano: A Torus Assignment for an Interconnection Network Recursive Diagonal Torus. ISPAN 1999: 74-79
36EEFumiharu Morisawa, Daisuke Kawakami, Kensuke Tanaka, Hideharu Amano: An Educational System of LSI Design with Free-Wares for VDEC. MSE 1999: 61-62
35 Junji Yamamoto, Takashi Fujiwara, T. Komeda, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano: Performance evaluation of SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture. Parallel Computing 25(9): 1081-1103 (1999)
1998
34 Takashi Midorikawa, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano: The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip. ASP-DAC 1998: 337-338
33 Hideharu Amano, Yuichiro Shibata: Reconfigurable Systems: Activities in Asia and South Pacific (Embedded Tutorial). ASP-DAC 1998: 453-457
32 Yuichiro Shibata, Hidenori Miyazaki, Xiao-ping Ling, Hideharu Amano: HOSMII: A Virtual Hardware Integrated with DRAM. IPPS/SPDP Workshops 1998: 85-90
31EEOu Yamamoto, Takuya Terasawa, Hideharu Amano: An analysis of fairness and overhead in the arbitration protocol of the IEEE Futurebus standard. Systems and Computers in Japan 29(13): 66-77 (1998)
1997
30EEToru Kisuki, Masaki Wakabayashi, Junji Yamamoto, Keisuke Inoue, Hideharu Amano: Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors. Euro-Par 1997: 793-797
29 Kazumasa Nukata, Yuichiro Shibata, Hideharu Amano, Yuichiro Anzai: A reconfigurable sensor-data processing system for personal robots. FPL 1997: 491-500
28 Akira Funahashi, Toshihiro Hanawa, Hideharu Amano, Tomohiro Kudoh: Adaptive Routing on the Recursive Diagonal Torus. ISHPC 1997: 171-182
27EEXiaoshe Dong, Tomohiro Kudoh, Hideharu Amano: Wavelength Division Multiple Access Ring - Virtual Topology on a Simple Ring Network. ISPAN 1997: 30-36
26 Xiao-ping Ling, Yuichiro Shibata, Hidenori Miyazaki, Hideharu Amano, Koichi Higure: Total System Image of the Reconfigurable Machine WASMII. PDPTA 1997: 1092-1096
25EETakuya Terasawa, Keisuke Inoue, Hitoshi Kurosawa, Hideharu Amano: A study on snoop cache systems for single-chip multiprocessors. Systems and Computers in Japan 28(2): 62-72 (1997)
1996
24 Keisuke Inoue, Toru Kisuki, Michitaka Okuno, Etsuko Shimizu, Takuya Terasawa, Hideharu Amano: ATTEMPT-1: A Reconfigurable Multiprocessor Testbed. FPL 1996: 200-209
23 Yuichiro Shibata, Xiao-ping Ling, Hideharu Amano: An Emulation System of the WASMII: A Data Driven Computer on a Virtual Hardware. FPL 1996: 55-64
1995
22 Tomohiro Kudoh, Hideharu Amano, Takashi Matsumoto, Kei Hiraki, Yulu Yang, Katsunobu Nishimura, Koichi Yoshimura, Yasuhito Fukushima: Hierarchical Bit-Map Directory Schemes on the RDT Interconnection Network for a Massively Parallel Processor JUMP-1. ICPP (1) 1995: 186-193
21 Junji Yamamoto, D. Hattori, Jun-ichi Yamato, T. Tokuyoshi, Y. Yamaguchi, Hideharu Amano: A Preprocessing System of the EULASH: An Environment for Efficient use of Multiprocessors with Local Memory. Parallel and Distributed Computing and Systems 1995: 68-71
20EEKyotaro Suzuki, Hideharu Amano, Yoshiyasu Takefuji: Neural network parallel computing for multi-layer channel routing problems. Neurocomputing 8(2): 141-156 (1995)
19 Takuya Terasawa, Ou Yamamoto, Tomohiro Kudoh, Hideharu Amano: A Performance Evaluation of the Multiprocessor Testbed ATTEMPT-0. Parallel Computing 21(5): 701-730 (1995)
1994
18 Xiao-yu Chen, Xiao-ping Ling, Hideharu Amano: Software Environment for WASMII: a Data Driven Machine with a Virtual Hardware. FPL 1994: 208-219
17 Toshihiro Hanawa, Hideharu Amano, Yoshifumi Fujikawa: Multistage Interconnection Networks with Multiple Outlets. ICPP (1) 1994: 1-8
16 Masashi Sasahara, Jun Terada, Luo Zhou, Kalidou Gaye, Jun-ichi Yamato, Satoshi Ogura, Hideharu Amano: SNAIL: A Multiprocessor Based on the Simple Serial Synchronized Multistage Interconnection Network Architecture. ICPP (1) 1994: 117-120
1993
15EEXiao-ping Ling, Hideharu Amano: Performance evaluation of WASMII: a data driven computer on a virtual hardware. PARLE 1993: 610-621
14 Yulu Yang, Hideharu Amano, Hidetomo Shibamura, Toshinori Sueyoshi: Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers. SPDP 1993: 591-595
1992
13 Tomohiro Kudoh, Tetsuro Kimura, Hideharu Amano, Takuya Terasawa: A Parallel Logic Simulation Algorithm Based on Query. ICPP (3) 1992: 262-266
12 Hideharu Amano, Luo Zhou, Kalidou Gaye: SSS (Simple Serial Synchronized)-MIN: A Novel Multi Stage Interconnection Architecture for Multiprocessors. IFIP Congress (1) 1992: 571-577
1991
11 Hideharu Amano, Kalidou Gaye: A Batcher Double Omega Network with Combining. ICPP (1) 1991: 718-719
1990
10 Hideharu Amano: A Fault Tolerant Batcher Network. ICPP (1) 1990: 441-444
9 Hideharu Amano, Taisuke Boku, Tomohiro Kudoh: (SM)²-II: A Large-Scale Multiprocessor for Sparse Matrix Calculations. IEEE Trans. Computers 39(7): 889-905 (1990)
1989
8 Hideharu Amano, Takuya Terasawa, Tomohiro Kudoh: Cache with Synchronization Mechanism. IFIP Congress 1989: 1001-1006
7 Jun Miyazaki, Kenji Takeda, Hideharu Amano, Hideo Aiso: A New Version of a Parallel Production System Machine, MANJI-II. IWDM 1989: 317-330
6EEXiao-ping Ling, Hideharu Amano: A static scheduling system for a parallel machine (SM)2-II. PARLE (1) 1989: 118-135
1988
5 Taisuke Boku, Shigehiro Nomura, Hideharu Amano: IMPULSE: A High Performance Processing Unit for Multiprocessors for Scientific Calculation. ISCA 1988: 365-372
1987
4 Jun Miyazaki, Hideharu Amano, Kenji Takeda, Hideo Aiso: A Shared Memory Architecture for MANJI Production System Machine. IWDM 1987: 517-531
1986
3EEChizuko Saito, Hideharu Amano, Tomohiro Kudoh, Hideo Aiso: An Adaptable Cluster Structure of (SM)²-II. CONPAR 1986: 53-60
1985
2 Hideharu Amano, Taisuke Boku, Tomohiro Kudoh, Hideo Aiso: (SM)²-II: A New Version of the Sparse Matrix Solving Machine. ISCA 1985: 100-107
1983
1 Hideharu Amano, Takaichi Yoshida, Hideo Aiso: (SM)2: Sparse Matrix Solving Machine ISCA 1983: 213-220

Coauthor Index

1Shohei Abe [97] [101] [102] [103] [104] [109] [110] [114]
2Hideo Aiso [1] [2] [3] [4] [7] [75]
3Yoshiaki Ajioka [128] [132]
4S. Akutsu [43]
5Jose Miguel Montanana Aliaga [152]
6Kenichiro Anjo [70] [71] [78] [81] [82] [97] [104] [106]
7Yuichiro Anzai [29]
8Masatoshi Arai [128] [132]
9Toru Awashima [81] [97] [104]
10Taisuke Boku [2] [5] [9]
11Xiao-yu Chen [18]
12Katsuaki Deguchi [81] [101] [102] [103] [104]
13Yasunori Dohi [76]
14Xiaoshe Dong [27] [41]
15Qin Fan [37]
16Taro Fujii [50] [79]
17Yoshifumi Fujikawa [17]
18Takashi Fujiwara [35] [40]
19Tomonori Fukushima [69] [80] [84] [93] [99] [100]
20Yasuhito Fukushima [22]
21Akira Funahashi [28] [37] [55] [56] [57] [58] [63] [93] [96] [99] [100] [112] [113] [126] [130] [140] [157]
22K. Furuta [50]
23Kalidou Gaye [11] [12] [16]
24Hirotaka Hakozaki [76]
25Yoshihiro Hamada [45] [52] [60] [62] [89] [92] [122]
26Toshihiro Hanawa [17] [28] [34] [35] [67] [85] [91]
27Hiroshi Harada [73] [74]
28K. Harasawa [43]
29Yohei Hasegawa [81] [97] [101] [102] [103] [109] [110] [114] [116] [127] [131] [139] [141] [143] [144] [156]
30Tasunori Hashida [151]
31D. Hattori [21]
32Koichi Higure [26] [39]
33Keiichiro Hirai [141]
34Kei Hiraki [22]
35Noriko Hiroi [93] [96] [99] [100] [112] [113] [126] [130] [140] [157]
36Tomoyuki Hiroyasu [152]
37D. Frank Hsu [138] [150]
38Daisuke Ikebuchi [139]
39Masashi Imai [151]
40Hideki Imashiro [62]
41Keisuke Inoue [24] [25] [30] [42]
42Takeshi Inuo [79]
43M. Ishii [44]
44K. Ishikawa [114]
45Tomoya Ishimori [157]
46Keisuke Iwai [39] [40] [47]
47Naoki Iwanaga [96] [99] [100] [112] [113] [126] [130]
48Yow Iwaoka [93] [96] [99] [100] [113] [126] [130]
49Tetsu Izawa [92]
50Naoyuki Izu [64]
51Kazuki Joe [75]
52Akiya Jouraku [55] [56] [57] [58] [61] [63] [68] [71] [72] [78] [82] [86] [87] [94] [95] [106] [120]
53Takayuki Kamei [34] [35]
54Hirokazu Kami [79]
55Jun Kanai [139]
56Takamasa Kanamori [128] [132]
57Naoto Kaneko [65] [81]
58Toshihiro Kashima [139]
59Masaru Kato [143] [144]
60Naohiro Katsura [109] [116] [153]
61Takahiro Kawaguchi [40] [53]
62Daisuke Kawakami [36] [59]
63Masahiko Kawamura [83]
64Jo Kei [139]
65Tetsuro Kimura [13]
66Toru Kisuki [24] [30]
67Akira Kitamura [89] [92] [121] [122]
68Hiroaki Kitano [93] [96] [99] [100] [112] [113] [126] [130] [140]
69Toshiro Kitaoka [70]
70Michihiro Koibuchi [56] [57] [58] [61] [63] [68] [72] [78] [82] [86] [87] [88] [90] [94] [95] [106] [107] [108] [111] [115] [118] [120] [123] [124] [125] [129] [136] [137] [138] [142] [146] [149] [150] [152] [154] [155]
71Toshinori Kojima [113] [126] [130]
72Yu Kojima [139]
73T. Komeda [35]
74Masaaki Kondo [139] [151]
75Daisuke Konno [128] [132]
76Kenichi Kono [72]
77T. Kudo [44]
78Tomohiro Kudoh [2] [3] [8] [9] [13] [19] [22] [27] [28] [41] [43] [45] [46] [52] [54] [60] [62] [73] [74] [111] [119]
79Hitoshi Kurosawa [25] [49] [51]
80Shunsuke Kurotaki [81] [109] [114]
81Xiao-ping Ling [6] [15] [18] [23] [26] [32] [38] [39]
82Hiroki Masuda [151]
83N. Matsudaira [43]
84Takashi Matsumoto [22]
85Hiroki Matsutani [90] [94] [97] [107] [108] [115] [118] [123] [125] [129] [136] [137] [138] [142] [146] [149] [150] [152] [153] [154] [155]
86Takashi Midorikawa [34] [67] [77] [85]
87Toshiya Minai [91]
88Kenichi Miura [124]
89Yasuo Miyabe [92] [121]
90Tomotaka Miyashiro [92] [121]
91Hidenori Miyazaki [26] [32] [39]
92Jun Miyazaki [4] [7]
93Fumiharu Morisawa [36]
94Masato Motomura [50] [81]
95Hironori Nakajo [44] [45] [52] [60] [62] [76] [89] [92] [121] [122]
96Hiroshi Nakamura [139] [151]
97Tadao Nakamura [148]
98Takuro Nakamura [109] [114] [141]
99Mitsutaka Nakata [139] [151]
100Masasige Nakatake [76]
101Mitaro Namiki [139] [151]
102Tomomichi Nanba [128] [132]
103Hiroaki Nishi [43] [45] [46] [52] [54] [55] [60] [73] [74] [89] [119]
104Yuri Nishikawa [113] [124] [126] [130] [140] [157]
105Katsunobu Nishimura [22] [82]
106Shinji Nishimura [43]
107Takashi Nishimura [109] [114] [141]
108Shigehiro Nomura [5]
109Kazumasa Nukata [29]
110Satoshi Ogura [16]
111Kiyoshi Oguri [99] [126] [157]
112Atushi Ohta [122]
113Michitaka Okuno [24]
114Yasunori Osana [69] [80] [84] [93] [96] [99] [100] [112] [113] [126] [130] [140] [157]
115Tomohiro Otsuka [73] [74] [88] [92] [95] [111] [119] [154]
116Timothy Mark Pinkston [137]
117Chizuko Saito [3]
118Yoshiki Saito [141]
119Katsuto Sakamoto [40]
120Toru Sano [143]
121Masashi Sasahara [16]
122Naomi Seki [139] [151] [156]
123Hidetomo Shibamura [14]
124Yuichiro Shibata [23] [26] [29] [32] [33] [38] [39] [47] [48] [49] [50] [51] [59] [93] [96] [99] [100] [112] [113] [126] [130] [140] [157]
125Masayoshi Shigeno [67] [85]
126Etsuko Shimizu [24]
127Toshiaki Shirai [139] [151]
128Daisuke Shiraishi [67] [85]
129Toshinori Sueyoshi [14] [55]
130Masato Sumiyoshi [77]
131Tetsuya Sunata [139]
132Kyotaro Suzuki [20]
133Masayasu Suzuki [79] [81] [98] [102] [103] [104] [110] [117]
134Noriaki Suzuki [66] [81]
135Takayuki Suzuki [53]
136Atsushi Takayama [39] [47]
137Kenji Takeda [4] [7]
138Seidai Takeda [139] [151]
139Yoshiyasu Takefuji [20]
140Noboru Tanabe [45] [52] [60] [62] [76] [89] [92] [119] [121] [122]
141Yasuki Tanabe [67] [77] [85] [91]
142Kensuke Tanaka [36]
143Koji Tasho [46] [54]
144Jun Terada [16]
145Takuya Terasawa [8] [13] [19] [24] [25] [31]
146Takeo Toi [81]
147T. Tokuyoshi [21]
148Junichiro Tsuchiya [64] [73] [74] [119]
149Satoshi Tsutsumi [143]
150Shunsuke Tsutsumi [114]
151Satoshi Tsutsusmi [141]
152Vu Manh Tuan [109] [110] [116] [131] [133] [134] [145] [147] [153]
153Vasutan Tunbunheng [98] [117] [135] [141]
154Masaki Uno [48] [50]
155Kimiyoshi Usami [139] [151] [156]
156Alexander V. Veidenbaum [75]
157Kazutoshi Wakabayashi [81]
158Masaki Wakabayashi [30] [42]
159Daihan Wang [115] [118] [129] [136] [142] [146] [149]
160Konosuke Watanabe [64] [68] [72] [73] [74] [88] [92] [119]
161Takafumi Watanabe [152]
162Hui Xu [156]
163Hideki Yamada [126] [130] [140] [157]
164Yutaka Yamada [78] [81] [82] [94] [106] [150]
165Y. Yamaguchi [21]
166Junji Yamamoto [21] [30] [35] [45] [46] [52] [60] [62] [73] [74] [119]
167Ou Yamamoto [19] [31] [49] [51]
168Jun-ichi Yamato [16] [21]
169Yulu Yang [14] [22] [37] [55]
170Tomonori Yokoyama [64]
171Takaichi Yoshida [1]
172Saito Yoshiki [156]
173Masato Yoshimi [80] [93] [96] [99] [100] [112] [113] [115] [124] [126] [130] [140] [157]
174Koichi Yoshimura [22]
175Tsutomu Yoshinaga [155]
176Lei Zhao [139] [156]
177Luo Zhou [12] [16]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)