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* | 2009 | |
---|---|---|

92 | EE | Shiyan Hu, Zhuo Li, Charles J. Alpert: A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion. DAC 2009: 424-429 |

2008 | ||

91 | EE | Michael D. Moffitt, David A. Papa, Zhuo Li, Charles J. Alpert: Path smoothing via discrete optimization. DAC 2008: 724-727 |

90 | EE | Shiyan Hu, Zhuo Li, Charles J. Alpert: A polynomial time approximation scheme for timing constrained minimum cost layer assignment. ICCAD 2008: 112-115 |

89 | EE | Tao Luo, David A. Papa, Zhuo Li, Chin-Ngai Sze, Charles J. Alpert, David Z. Pan: Pyramids: an efficient computational geometry-based approach for timing-driven placement. ICCAD 2008: 204-211 |

88 | EE | David A. Papa, Tao Luo, Michael D. Moffitt, Chin-Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov: RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. ISPD 2008: 2-9 |

87 | EE | Zhuo Li, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia: Fast interconnect synthesis with layer assignment. ISPD 2008: 71-77 |

86 | EE | David A. Papa, Tao Luo, Michael D. Moffitt, Chin-Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov: RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2156-2168 (2008) |

2007 | ||

85 | EE | Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia: Hippocrates: First-Do-No-Harm Detailed Placement. ASP-DAC 2007: 141-146 |

84 | EE | Shrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud: Fast Electrical Correction Using Resizing and Buffering. ASP-DAC 2007: 553-558 |

83 | EE | Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu: RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. DAC 2007: 453-458 |

82 | EE | Charles J. Alpert, Chris C. N. Chu, Paul G. Villarrubia: The coming of age of physical synthesis. ICCAD 2007: 246-249 |

81 | EE | Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi: Probabilistic Congestion Prediction with Partial Blockages. ISQED 2007: 841-846 |

80 | EE | Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz: The nuts and bolts of physical synthesis. SLIP 2007: 89-94 |

79 | EE | Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin-Ngai Sze: Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2009-2022 (2007) |

78 | EE | Haoxing Ren, David Z. Pan, Charles J. Alpert, Paul G. Villarrubia, Gi-Joon Nam: Diffusion-Based Placement Migration With Application on Legalization. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2158-2172 (2007) |

77 | EE | Chin-Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi: Path-Based Buffer Insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1346-1355 (2007) |

2006 | ||

76 | EE | Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze: Fast algorithms for slew constrained minimum cost buffering. DAC 2006: 308-313 |

75 | EE | Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang: Timing-driven Steiner trees are (practically) free. DAC 2006: 389-392 |

74 | EE | Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng: A Fast Hierarchical Quadratic Placement Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 678-691 (2006) |

73 | EE | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze: Accurate estimation of global buffer delay within a floorplan. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1140-1145 (2006) |

2005 | ||

72 | EE | Charles J. Alpert, Gi-Joon Nam, Paul Villarribua, Mehmet Can Yildiz: Placement stability metrics. ASP-DAC 2005: 1144-1147 |

71 | EE | Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi: Making fast buffer insertion even faster via approximation techniques. ASP-DAC 2005: 13-18 |

70 | EE | Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi: Path based buffer insertion. DAC 2005: 509-514 |

69 | EE | Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia: Diffusion-based placement migration. DAC 2005: 515-520 |

68 | Tao Luo, Haoxing Ren, Charles J. Alpert, David Zhigang Pan: Computational geometry based placement migration. ICCAD 2005: 41-47 | |

67 | Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert: Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD 2005: 592-596 | |

66 | EE | Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia: A semi-persistent clustering technique for VLSI circuit placement. ISPD 2005: 200-207 |

65 | EE | Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz: The ISPD2005 placement contest and benchmark suite. ISPD 2005: 216-220 |

64 | EE | Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif: An efficient surface-based low-power buffer insertion algorithm. ISPD 2005: 86-93 |

2004 | ||

63 | Charles J. Alpert, Patrick Groeneveld: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004 ACM 2004 | |

62 | EE | Cliff C. N. Sze, Jiang Hu, Charles J. Alpert: A place and route aware buffered Steiner tree construction. ASP-DAC 2004: 355-360 |

61 | EE | Weiping Shi, Zhuo Li, Charles J. Alpert: Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. ASP-DAC 2004: 609-614 |

60 | EE | Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay: Fast and flexible buffer trees that navigate the physical layout environment. DAC 2004: 24-29 |

59 | EE | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze: Accurate estimation of global buffer delay within a floorplan. ICCAD 2004: 706-711 |

58 | EE | Charles J. Alpert, Milos Hrkic, Stephen T. Quay: A fast algorithm for identifying good buffer insertion candidate locations. ISPD 2004: 47-52 |

57 | EE | Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 136-141 (2004) |

56 | EE | Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan: Closed-form delay and slew metrics made easy. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1661-1669 (2004) |

55 | EE | Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert: A delay metric for RC circuits based on the Weibull distribution. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 443-447 (2004) |

54 | EE | Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan: Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 509-516 (2004) |

53 | EE | Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze: Porosity-aware buffered Steiner tree construction. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 517-526 (2004) |

2003 | ||

52 | Massoud Pedram, Charles J. Alpert: Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003 ACM 2003 | |

51 | EE | Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan: Delay and slew metrics using the lognormal distribution. DAC 2003: 382-385 |

50 | EE | Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay: Porosity aware buffered steiner tree construction. ISPD 2003: 158-165 |

49 | EE | Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan: Closed form expressions for extending step delay and slew metrics to ramp inputs. ISPD 2003: 24-31 |

48 | EE | Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia: Effective free space management for cut-based placement via analytical constraint generation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1343-1353 (2003) |

47 | EE | Soha Hassoun, Charles J. Alpert: Optimal path routing in single- and multiple-clock domain systems. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1580-1588 (2003) |

46 | EE | Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky: Minimum buffered routing with bounded capacitive load for slew rate and reliability control. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 241-253 (2003) |

45 | EE | Charles J. Alpert, Sachin S. Sapatnekar: Guest editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 385-386 (2003) |

44 | EE | Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham: Buffer insertion with adaptive blockage avoidance. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 492-498 (2003) |

43 | EE | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia: A practical methodology for early buffer and wire resource allocation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 573-583 (2003) |

2002 | ||

42 | David P. LaPotin, Charles J. Alpert, John Lillis: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002 ACM 2002 | |

41 | EE | Soha Hassoun, Charles J. Alpert, Meera Thiagarajan: Optimal buffered routing path constructions for single and multiple clock domain systems. ICCAD 2002: 247-253 |

40 | EE | Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert: A delay metric for RC circuits based on the Weibull distribution. ICCAD 2002: 620-624 |

39 | EE | Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia: Free space management for cut-based placement. ICCAD 2002: 746-751 |

38 | EE | Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD 2002: 104-109 |

37 | EE | Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham: Buffer insertion with adaptive blockage avoidance. ISPD 2002: 92-97 |

36 | EE | Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan: PERI: a technique for extending delay and slew metrics to ramp inputs. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 57-62 |

35 | EE | Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay: Correction to "interconnect synthesis without wire tapering". IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 497-497 (2002) |

34 | EE | Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert: Probability-driven routing in a datapath environment. Integration 31(2): 159-182 (2002) |

2001 | ||

33 | EE | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia: A Practical Methodology for Early Buffer and Wire Resource Allocation. DAC 2001: 189-194 |

32 | EE | Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky: Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. ICCAD 2001: 408- |

31 | EE | Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar: Steiner tree optimization for buffers. Blockages and bays. ISCAS (5) 2001: 399-402 |

30 | EE | Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia: Buffered Steiner trees for difficult instances. ISPD 2001: 4-9 |

29 | EE | Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay: Interconnect synthesis without wire tapering. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 90-104 (2001) |

28 | EE | Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar: Steiner tree optimization for buffers, blockages, and bays. IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 556-562 (2001) |

27 | EE | Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap: RC delay metrics for performance optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 571-582 (2001) |

2000 | ||

26 | Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan: An "Effective" Capacitance Based Delay Metric for RC Interconnect. ICCAD 2000: 229-234 | |

25 | EE | Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert: Datapath routing based on a decongestion metric. ISPD 2000: 122-127 |

24 | EE | Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap: A two moment RC delay metric for performance optimization. ISPD 2000: 69-74 |

23 | EE | Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Hypergraph partitioning with fixed vertices [VLSI CAD]. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 267-272 (2000) |

1999 | ||

22 | EE | Charles J. Alpert, Anirudh Devgan, Stephen T. Quay: Buffer Insertion with Accurate Gate and Interconnect Delay Computation. DAC 1999: 479-484 |

21 | EE | Charles J. Alpert, Anirudh Devgan, Stephen T. Quay: Is wire tapering worthwhile? ICCAD 1999: 430-436 |

20 | EE | Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov: Partitioning with terminals: a "new" problem and new benchmarks. ISPD 1999: 151-157 |

19 | EE | Charles J. Alpert, Andrew B. Kahng, So-Zen Yao: Spectral Partitioning with Multiple Eigenvectors. Discrete Applied Mathematics 90(1-3): 3-26 (1999) |

18 | EE | Charles J. Alpert, Anirudh Devgan, Stephen T. Quay: Buffer insertion for noise and delay optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1633-1645 (1999) |

1998 | ||

17 | EE | Charles J. Alpert, Anirudh Devgan, Stephen T. Quay: Buffer Insertion for Noise and Delay Optimization. DAC 1998: 362-367 |

16 | EE | Charles J. Alpert: The ISPD98 circuit benchmark suite. ISPD 1998: 80-85 |

15 | EE | Charles J. Alpert, Tony F. Chan, Andrew B. Kahng, Igor L. Markov, Pep Mulet: Faster minimization of linear wirelength for global placement. IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 3-13 (1998) |

14 | EE | Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng: Multilevel circuit partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 655-667 (1998) |

1997 | ||

13 | EE | Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng: Multilevel Circuit Partitioning. DAC 1997: 530-533 |

12 | EE | Charles J. Alpert, Anirudh Devgan: Wire Segmenting for Improved Buffer Insertion. DAC 1997: 588-593 |

11 | EE | Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Igor L. Markov, Kenneth Yan: Quadratic Placement Revisited. DAC 1997: 752-757 |

10 | EE | Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, Kenneth Yan: Faster minimization of linear wirelength for global placement. ISPD 1997: 4-11 |

1996 | ||

9 | EE | Charles J. Alpert, Andrew B. Kahng: A general framework for vertex orderings with applications to circuit clustering. IEEE Trans. VLSI Syst. 4(2): 240-246 (1996) |

1995 | ||

8 | EE | Charles J. Alpert, So-Zen Yao: Spectral Partitioning: The More Eigenvectors, The Better. DAC 1995: 195-200 |

7 | EE | Charles J. Alpert, Andrew B. Kahng: Multiway partitioning via geometric embeddings, orderings, and dynamic programming. IEEE Trans. on CAD of Integrated Circuits and Systems 14(11): 1342-1358 (1995) |

6 | EE | Charles J. Alpert, T. C. Hu, Dennis J.-H. Huang, Andrew B. Kahng, David R. Karger: Prim-Dijkstra tradeoffs for improved performance-driven routing tree design. IEEE Trans. on CAD of Integrated Circuits and Systems 14(7): 890-896 (1995) |

1994 | ||

5 | EE | Charles J. Alpert, Andrew B. Kahng: Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming. DAC 1994: 652-657 |

4 | EE | Charles J. Alpert, Andrew B. Kahng: A general framework for vertex orderings, with applications to netlist clustering. ICCAD 1994: 63-67 |

1993 | ||

3 | EE | Charles J. Alpert, Andrew B. Kahng: Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning. DAC 1993: 743-748 |

2 | Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh: Minimum Density Interconneciton Trees. ISCAS 1993: 1865-1868 | |

1 | Charles J. Alpert, T. C. Hu, Jen-Hsin Huang, Andrew B. Kahng: A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing. ISCAS 1993: 1869-1872 |