| 2007 |
|---|
| 6 | EE | Allon Adir,
Sigal Asaf,
Laurent Fournier,
Itai Jaeger,
Ofer Peled:
A Framework for the Validation of Processor Architecture Compliance.
DAC 2007: 902-905 |
| 2005 |
|---|
| 5 | EE | Allon Adir,
Hezi Azatchi,
Eyal Bin,
Ofer Peled,
Kirill Shoikhet:
A generic micro-architectural test plan approach for microprocessor verification.
DAC 2005: 769-774 |
| 4 | EE | Allon Adir,
Yaron Arbetman,
Bella Dubrov,
Yossi Lichtenstein,
Michal Rimon,
Michael Vinov,
Massimo A. Calligaro,
Andrew Cofler,
Gabriel Duffy:
VLIW: a case study of parallelism verification.
DAC 2005: 779-782 |
| 2004 |
|---|
| 3 | EE | Allon Adir,
Eli Almog,
Laurent Fournier,
Eitan Marcus,
Michal Rimon,
Michael Vinov,
Avi Ziv:
Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification.
IEEE Design & Test of Computers 21(2): 84-93 (2004) |
| 2003 |
|---|
| 2 | EE | Allon Adir,
Roy Emek,
Yoav Katz,
Anatoly Koyfman:
DeepTrans - A Model-based Approach to Functional Verification of Address Translation Mechanisms.
MTV 2003: 3-6 |
| 1 | EE | Allon Adir,
Hagit Attiya,
Gil Shurek:
Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture.
IEEE Trans. Parallel Distrib. Syst. 14(5): 502-515 (2003) |
