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Jacob A. Abraham Vis

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*2009
248EESavithri Sundareswaran, Rajendran Panda, Jacob A. Abraham, Yun Zhang, Amit Mittal: Characterization of sequential cells for constraint sensitivities. ISQED 2009: 74-79
247EESriram Sambamurthy, Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham: Functionally valid gate-level peak power estimation for processors. ISQED 2009: 753-758
246EEVinod Viswanath, Shobha Vasudevan, Jacob A. Abraham: Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL. VLSI Design 2009: 77-82
2008
245EESankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Suriyaprakash Natarajan: On efficient generation of instruction sequences to test for delay defects in a processor. ACM Great Lakes Symposium on VLSI 2008: 279-284
244EERajeshwary Tayade, Sani R. Nassif, Jacob A. Abraham: Analytical model for the impact of multiple input switching noise on timing. ASP-DAC 2008: 514-517
243EERamtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche: A low-cost concurrent error detection technique for processor control logic. DATE 2008: 897-902
242EEJacob A. Abraham: Implications of Technology Trends on System Dependability. DATE 2008: 940
241EEBaker Mohammad, Stephen Bijansky, Adnan Aziz, Jacob A. Abraham: Adaptive SRAM memory for low power and high yield. ICCD 2008: 176-181
240EEBaker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham: Cache Design for Low Power and High Yield. ISQED 2008: 103-107
239EESavithri Sundareswaran, Jacob A. Abraham, Alexandre Ardelea, Rajendran Panda: Characterization of Standard Cells for Intra-Cell Mismatch Variations. ISQED 2008: 213-219
238EESavithri Sundareswaran, Lucie Nechanicka, Rajendran Panda, Sergey Gavrilov, Roman Solovyev, Jacob A. Abraham: A timing methodology considering within-die clock skew variations. SoCC 2008: 351-356
237EESriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri: A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits. VLSI Design 2008: 521-526
236EEChaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham: Low Cost RF Receiver Parameter Measurement with On-Chip Amplitude Detectors. VTS 2008: 203-208
235EEByoungho Kim, Nash Khouzam, Jacob A. Abraham: Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits. VTS 2008: 293-298
234EEQingqi Dou, Jacob A. Abraham: Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems. VTS 2008: 3-8
233EEJoonsung Park, Hongjoong Shin, Jacob A. Abraham: Parallel Loopback Test of Mixed-Signal Circuits. VTS 2008: 309-316
232EERamyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka: Performance-Optimized Design for Parametric Reliability. J. Electronic Testing 24(1-3): 129-141 (2008)
231EERamyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu: Controllability of Static CMOS Circuits for Timing Characterization. J. Electronic Testing 24(5): 481-496 (2008)
2007
230EEJen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham: Reducing verification overhead with RTL slicing. ACM Great Lakes Symposium on VLSI 2007: 399-404
229EERajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham: Estimating path delay distribution considering coupling noise. ACM Great Lakes Symposium on VLSI 2007: 61-66
228EESankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab: Automatic Generation of Instructions to Robustly Test Delay Defects in Processors. European Test Symposium 2007: 173-178
227EEChaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham: Built-In Test of RF Mixers Using RF Amplitude Detectors. ISQED 2007: 404-409
226EEJoonsung Park, Hongjoong Shin, Jacob A. Abraham: Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series Model. ISQED 2007: 495-500
225EERajeshwary Tayade, Savithri Sundareswaran, Jacob A. Abraham: Small-Delay Defect Detection in the Presence of Process Variations. ISQED 2007: 711-716
224EEShobha Vasudevan, Vinod Viswanath, Jacob A. Abraham: Efficient Microprocessor Verification using Antecedent Conditioned Slicing. VLSI Design 2007: 43-49
223EEJacob A. Abraham, Daniel G. Saab: Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs. VLSI Design 2007: 6
222EEByoungho Kim, Zhenhai Fu, Jacob A. Abraham: Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications. VTS 2007: 291-296
221EEShobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham: Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. IEEE Trans. Computers 56(10): 1401-1414 (2007)
220EEShobha Vasudevan, E. Allen Emerson, Jacob A. Abraham: Improved verification of hardware designs through antecedent conditioned slicing. STTT 9(1): 89-101 (2007)
2006
219EEQingqi Dou, Jacob A. Abraham: Jitter decomposition in ring oscillators. ASP-DAC 2006: 285-290
218EEVinod Viswanath, Jacob A. Abraham, Warren A. Hunt Jr.: Automatic insertion of low power annotations in RTL for pipelined microprocessors. DATE 2006: 496-501
217EERamyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka: Adaptive Design for Performance-Optimized Robustness. DFT 2006: 3-11
216EEByoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham: Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters. European Test Symposium 2006: 199-204
215EERamtilak Vemu, Jacob A. Abraham: CEDA: Control-flow Error Detection through Assertions. IOLTS 2006: 151-158
214EEQingqi Dou, Jacob A. Abraham: Jitter Decomposition by Time Lag Correlation. ISQED 2006: 525-530
213EEShobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu: Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. MEMOCODE 2006: 71-80
212EESriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri: Delay Constrained Register Transfer Level Dynamic Power Estimation. PATMOS 2006: 36-46
211EEQiang Qiang, Daniel G. Saab, Jacob A. Abraham: Checking Nested Properties Using Bounded Model Checking and Sequential ATPG. VLSI Design 2006: 225-230
210EERamyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham: A Scheme for On-Chip Timing Characterization. VTS 2006: 24-29
209EEHongjoong Shin, Byoungho Kim, Jacob A. Abraham: Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits. VTS 2006: 412-419
2005
208 Qiang Qiang, Daniel G. Saab, Jacob A. Abraham: An Emulation Model for Sequential ATPG-Based Bounded Model Checking. FPL 2005: 469-474
207EEQiang Qiang, Chia-Lun Chang, Daniel G. Saab, Jacob A. Abraham: Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core. ICCD 2005: 461-463
206EEShobha Vasudevan, E. Allen Emerson, Jacob A. Abraham: Efficient Model Checking of Hardware Using Conditioned Slicing. Electr. Notes Theor. Comput. Sci. 128(6): 279-294 (2005)
205EEJayanta Bhadra, Andrew K. Martin, Jacob A. Abraham: A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor. Formal Methods in System Design 27(1-2): 67-112 (2005)
2004
204EERamyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Jacob A. Abraham: On-chip delay measurement for silicon debug. ACM Great Lakes Symposium on VLSI 2004: 145-148
203EEHongjoong Shin, Hak-soo Yu, Jacob A. Abraham: LFSR-based BIST for analog circuits using slope detection. ACM Great Lakes Symposium on VLSI 2004: 316-321
202EEJi Hwan (Paul) Chun, Hak-soo Yu, Jacob A. Abraham: An efficient linearity test for on-chip high speed ADC and DAC using loop-back. ACM Great Lakes Symposium on VLSI 2004: 328-331
201EEJianhua Gan, Shouli Yan, Jacob A. Abraham: Effects of noise and nonlinearity on the calibration of a non-binary capacitor array in a successive approximation analog-to-digital converter. ASP-DAC 2004: 292-297
200 Shobha Vasudevan, Jacob A. Abraham: Static program transformations for efficient software model checking. IFIP Congress Topical Sessions 2004: 257-282
199 Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka: A low latency and low power dynamic Carry Save Adder. ISCAS (2) 2004: 477-480
198EERamyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu: Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing. ITC 2004: 1118-1127
197EEHak-soo Yu, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham: Performance Characterization of Mixed-Signal Circuits Using a Ternary Signal Representation. ITC 2004: 1389-1397
196EEAshwin Raghunathan, Ji Hwan (Paul) Chun, Jacob A. Abraham, Abhijit Chatterjee: Quasi-Oscillation Based Test for Improved Prediction of Analog Performance Parameters. ITC 2004: 252-261
195EEJing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham: On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. ITC 2004: 31-37
194EEAlper Sen, Vijay K. Garg, Jacob A. Abraham, Jayanta Bhadra: Formal Verification of a System-on-Chip Using Computation Slicing. ITC 2004: 810-819
193EEJing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham: On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. MTV 2004: 103-109
192EENarayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham: Towards The Complete Elimination of Gate/Switch Level Simulations. VLSI Design 2004: 115-
191EEVivekananda M. Vedula, Whitney J. Townsend, Jacob A. Abraham: Program Slicing for ATPG-Based Property Checking. VLSI Design 2004: 591-596
190EEAshwin Raghunathan, Hongjoong Shin, Jacob A. Abraham, Abhijit Chatterjee: Prediction of Analog Performance Parameters Using Oscillation Based Test. VTS 2004: 377-382
2003
189EEJianhua Gan, Shouli Yan, Jacob A. Abraham: Design and modeling of a 16-bit 1.5MSPS successive approximation ADC with non-binary capacitor array. ACM Great Lakes Symposium on VLSI 2003: 161-164
188EEWhitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.: Quadruple Time Redundancy Adders. DFT 2003: 250-256
187EEWhitney J. Townsend, Jacob A. Abraham, Parag K. Lala: On-Line Error Detecting Constant Delay Adder. IOLTS 2003: 17-
186EEArun Krishnamachary, Jacob A. Abraham: Effects of Multi-cycle Sensitization on Delay Tests. VLSI Design 2003: 137-142
185EEDaniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula: Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines. VLSI Design 2003: 243-248
184EEHak-soo Yu, Sungbae Hwang, Jacob A. Abraham: DSP-Based Statistical Self Test of On-Chip Converters. VTS 2003: 83-88
183EEKyoil Kim, Jacob A. Abraham, Jayanta Bhadra: Model Checking of Security Protocols with Pre-configuration. WISA 2003: 1-15
182EESungbae Hwang, Jacob A. Abraham: Test data compression and test time reduction using an embedded microprocessor. IEEE Trans. VLSI Syst. 11(5): 853-862 (2003)
181EEJeongjin Roh, Jacob A. Abraham: A comprehensive signature analysis scheme for oscillation-test. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1409-1423 (2003)
180EEVivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra, Raghuram S. Tupuri: A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages. J. Electronic Testing 19(2): 149-160 (2003)
2002
179EESungbae Hwang, Jacob A. Abraham: Selective-run built-in self-test using an embedded processor. ACM Great Lakes Symposium on VLSI 2002: 124-129
178EEArun Krishnamachary, Jacob A. Abraham: Test generation for resistive opens in CMOS. ACM Great Lakes Symposium on VLSI 2002: 65-70
177EEJason Baumgartner, Andreas Kuehlmann, Jacob A. Abraham: Property Checking via Structural Analysis. CAV 2002: 151-165
176EEJing Zeng, Magdy S. Abadir, Jacob A. Abraham: False timing path identification using ATPG techniques and delay-based information. DAC 2002: 562-565
175EEVivekananda M. Vedula, Jacob A. Abraham: FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis. DATE 2002: 730-735
174EEJacob A. Abraham, Arun Krishnamachary, Raghuram S. Tupuri: A Comprehensive Fault Model for Deep Submicron Digital Circuits. DELTA 2002: 360-364
173EEDaniel G. Saab, Fatih Kocan, Jacob A. Abraham: Massively Parallel/Reconfigurable Emulation Model for the D-algorithm. FPL 2002: 1172-1176
172EEKamalnayan Jayaraman, Vivekananda M. Vedula, Jacob A. Abraham: Native Mode Functional Self-Test Generation for Systems-on-Chip. ISQED 2002: 280-285
171EEJacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab: Verifying Properties Using Sequential ATPG. ITC 2002: 194-202
170EESungbae Hwang, Jacob A. Abraham: Optimal BIST Using an Embedded Microprocessor. ITC 2002: 736-745
169EEHak-soo Yu, Jacob A. Abraham: An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation. VLSI Design 2002: 441-446
168EEVivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra: Program Slicing for Hierarchical Test Generation. VTS 2002: 237-246
167EENarayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham: Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? VTS 2002: 275-280
166 Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita: Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. Formal Methods in System Design 21(1): 95-101 (2002)
2001
165EEJayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir: Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation. CHARME 2001: 386-402
164EEJing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham: Full chip false timing path identification: applications to the PowerPCTM microprocessors. DATE 2001: 514-519
163EEArun Krishnamachary, Jacob A. Abraham, Raghuram S. Tupuri: Timing Verification and Delay Test Generation for Hierarchical Designs. VLSI Design 2001: 157-162
162EEHenry Chang, Steve Dollens, Gordon Roberts, Charles E. Stroud, Mani Soma, Jacob A. Abraham: Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them? VTS 2001: 415-416
161EENarayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham: Design and Development Paradigm for Industrial Formal Verification CAD Tools. IEEE Design & Test of Computers 18(4): 26-35 (2001)
160EESuresh Seshadri, Jacob A. Abraham: Frequency Response Verification of Analog Circuits Using Global Optimization Techniques. J. Electronic Testing 17(5): 395-408 (2001)
2000
159EENina Saxena, Jacob A. Abraham, Avijit Saha: Causality based generation of directed test cases. ASP-DAC 2000: 503-508
158 Jeongjin Roh, Suresh Seshadri, Jacob A. Abraham: Verification of Delta-Sigma Converters Using Adaptive Regression Modeling. ICCAD 2000: 182-187
157EEHak-soo Yu, Songjun Lee, Jacob A. Abraham: An Adder Using Charge Sharing and its Application in DRAMs. ICCD 2000: 311-317
156EERaghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab: Hierarchical Test Generation for Systems On a Chip. VLSI Design 2000: 198-
155EERobert W. Sumners, Jayanta Bhadra, Jacob A. Abraham: Automatic Validation Test Generation Using Extracted Control Models. VLSI Design 2000: 312-
154EEJeongjin Roh, Jacob A. Abraham: A Mixed-Signal BIST Scheme with Time-Division Multiplexing (TDM) Comparator and Counters. VLSI Design 2000: 572-
153EEPradip Bose, Jacob A. Abraham: Performance and Functional Verification of Microprocessors. VLSI Design 2000: 58-63
152EEJeongjin Roh, Jacob A. Abraham: A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-Based Test. VTS 2000: 143-148
151EENarayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham: Validation of PowerPC(tm) Custom Memories using Symbolic Simulation. VTS 2000: 9-14
150EENarayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham: Validating PowerPC Microprocessor Custom Memories. IEEE Design & Test of Computers 17(4): 61-76 (2000)
149EEJian Shen, Jacob A. Abraham: An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation. J. Electronic Testing 16(1-2): 67-81 (2000)
1999
148EEJian Shen, Jacob A. Abraham, Dave Baker, Tony Hurson, Martin Kinkade, Gregorio Gervasio, Chen-chau Chu, Guanghui Hu: Functional Verification of the Equator MAP1000 Microprocessor. DAC 1999: 169-174
147EERaghuram S. Tupuri, Arun Krishnamachary, Jacob A. Abraham: Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor. DAC 1999: 647-652
146EERichard Raimi, Jacob A. Abraham: Detecting False Timing Paths: Experiments on PowerPC Microprocessors. DAC 1999: 737-741
145EERajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell: An Efficient Filter-Based Approach for Combinational Verification. DATE 1999: 132-137
144EEChia-Pin R. Liu, Jacob A. Abraham: Transistor Level Synthesis for Static CMOS Combinational Circuits. Great Lakes Symposium on VLSI 1999: 172-175
143EEDinos Moundanos, Jacob A. Abraham: Formal Checking of Properties in Complex Systems Using Abstractions. Great Lakes Symposium on VLSI 1999: 280-283
142EERobert W. Sumners, Jayanta Bhadra, Jacob A. Abraham: Improving Witness Search Using Orders on States. ICCD 1999: 452-457
141 Jacob A. Abraham: Position Statement: Increasing Test Coverage in a VLSI Design Course. ITC 1999: 1132
140 Jeongjin Roh, Jacob A. Abraham: Subband filtering scheme for analog and mixed-signal circuit testing. ITC 1999: 221-229
139 Kyung Tek Lee, Jacob A. Abraham: Critical path identification and delay tests of dynamic circuits. ITC 1999: 421-430
138 Rathish Jayabharathi, Manuel A. d'Abreu, Jacob A. Abraham: FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model. VLSI Design 1999: 232-235
137EEJian Shen, Jacob A. Abraham: Verification of Processor Microarchitectures. VTS 1999: 189-194
136EEZeyad Alkhalifa, V. S. S. Nair, Narayanan Krishnamurthy, Jacob A. Abraham: Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection. IEEE Trans. Parallel Distrib. Syst. 10(6): 627-641 (1999)
135EERajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell: An efficient filter-based approach for combinational verification. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1542-1557 (1999)
134EEDinos Moundanos, Jacob A. Abraham: On Design Validation Using Verification Technology. J. Electronic Testing 15(1-2): 173-189 (1999)
1998
133 Karl-Erwin Großpietsch, Jacob A. Abraham, Johannes Maier, Hans-Dieter Kochs, Michel Renovell: From Dependable Computing Systems to Computing for Integrated Dependable Systems? (Panel). FTCS 1998: 296-301
132EESujit Dey, Jacob A. Abraham, Yervant Zorian: High-level design validation and test. ICCAD 1998: 3
131EEJian Shen, Jacob A. Abraham: Native mode functional test generation for processors with applications to self test and design validation. ITC 1998: 990-999
130EEDinos Moundanos, Jacob A. Abraham: Using Verification Technology for Validation Coverage Analysis and Test Generation. VTS 1998: 254-259
129EEKyung Tek Lee, Clay Nordquist, Jacob A. Abraham: Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits. VTS 1998: 34-41
128 Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Hoskote: Abstraction Techniques for Validation Coverage Analysis and Test Generation. IEEE Trans. Computers 47(1): 2-14 (1998)
127EENaveena Nagi, Abhijit Chatterjee, Heebyung Yoon, Jacob A. Abraham: Signature analysis for analog and mixed-signal circuit test response compaction. IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 540-546 (1998)
126EEJian Shen, Jacob A. Abraham: Synthesis of Native Mode Self-Test Programs. J. Electronic Testing 13(2): 137-148 (1998)
125 Craig M. Chase, Prakash Arunachalam, Jacob A. Abraham: Memory Distribution: Techniques and Practice for CAD Applications. Parallel Computing 24(11): 1597-1615 (1998)
1997
124EEJun Yuan, Jian Shen, Jacob A. Abraham, Adnan Aziz: On Combining Formal and Informal Verification. CAV 1997: 376-387
123EERobert W. Sumners, Jacob A. Abraham: Hierarchical Specification of System Behavior. HASE 1997: 134-140
122 Raghuram S. Tupuri, Jacob A. Abraham: A Novel Functional Test Generation Method for Processors Using Commercial ATPG. ITC 1997: 743-752
121EERaghuram S. Tupuri, Jacob A. Abraham: A Novel Hierarchical Test Generation Method for Processors. VLSI Design 1997: 540-541
120EERathish Jayabharathi, Kyung Tek Lee, Jacob A. Abraham: A Novel Solution for Chip-Level Functional Timing Verification. VTS 1997: 137-142
119EEMagdy S. Abadir, Jacob A. Abraham, H. Hao, C. Hunter, Wayne M. Needham, Ron G. Walther: Microprocessor Test and Validation: Any New Avenues? VTS 1997: 458-464
118 Jawahar Jain, James R. Bitner, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell: Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions. IEEE Trans. Computers 46(11): 1230-1245 (1997)
117EEYatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos: Automatic verification of implementations of large circuits against HDL specifications. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 217-228 (1997)
116EEHoon Chang, Jacob A. Abraham: An Efficient Critical Path Tracing Algorithm for Designing High Performance Vlsi Systems. J. Electronic Testing 11(2): 119-129 (1997)
1996
115EEPrakash Arunachalam, Jacob A. Abraham, Manuel A. d'Abreu: A Hierarchal Approach for Power Reduction in VLSI Chips. Great Lakes Symposium on VLSI 1996: 182-
114 Sankaran Karthik, Mark Aitken, Glidden Martin, Srinivasu Pappula, Bob Stettler, Praveen Vishakantaiah, Manuel A. d'Abreu, Jacob A. Abraham: Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor. ITC 1996: 160-166
113 Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Hoskote: A Unified Framework for Design Validation and Manufacturing Test. ITC 1996: 875-884
112EERajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell: On More Efficient Combinational ATPG Using Functional Learning. VLSI Design 1996: 107-110
111EEJacob A. Abraham, Gopi Ganapathy: Practical Test and DFT for Next Generation VLSI. VLSI Design 1996: 3
110EEAbhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham: Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages. VTS 1996: 354-361
109EEHong Helena Zheng, Ashok Balivada, Jacob A. Abraham: A novel test generation approach for parametric faults in linear analog circuits . VTS 1996: 470-475
108EEAshok Balivada, Jin Chen, Jacob A. Abraham: Analog Testing with Time Response Parameters. IEEE Design & Test of Computers 13(2): 18-25 (1996)
107 V. S. S. Nair, Jacob A. Abraham, Prithviraj Banerjee: Efficient Techniques for the Analysis of Algorithm-Based Fault Tolerance (ABFT) Schemes. IEEE Trans. Computers 45(4): 499-503 (1996)
106EEDaniel G. Saab, Youssef Saab, Jacob A. Abraham: Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1278-1285 (1996)
105EEAshok Balivada, Hong Zheng, Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham: A unified approach for fault simulation of linear mixed-signal circuits. J. Electronic Testing 9(1-2): 29-41 (1996)
1995
104EEYatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell: Automated verification of temporal properties specified as state machines in VHDL. Great Lakes Symposium on VLSI 1995: 100-105
103EEYatin Vasant Hoskote, Dinos Moundanos, Jacob A. Abraham: Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors. ICCD 1995: 532-537
102EENaveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham: Efficient multisine testing of analog circuits. VLSI Design 1995: 234-238
101EEJawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross: Efficient variable ordering and partial representation algorithm. VLSI Design 1995: 81-86
100EEAshok Balivada, Yatin Vasant Hoskote, Jacob A. Abraham: Verification of transient response of linear analog circuits. VTS 1995: 42-47
99 Ghani A. Kanawati, Nasser A. Kanawati, Jacob A. Abraham: FERRARI: A Flexible Software-Based Fault and Error Injection System. IEEE Trans. Computers 44(2): 248-260 (1995)
1994
98EEJacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther: Microprocessor Testing: Which Technique is Best? (Panel). DAC 1994: 294
97 James R. Bitner, Jawahar Jain, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell: Efficient Algorithmic Circuit Verification Using Indexed BDDs. FTCS 1994: 266-275
96EEAbhijit Chatterjee, Jacob A. Abraham: RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults. ICCAD 1994: 340-343
95EEDaniel G. Saab, Youssef Saab, Jacob A. Abraham: Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0. ICCAD 1994: 40-43
94 Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham: A Signature Analyzer for Analog and Mixed-signal Circuits. ICCD 1994: 284-287
93 Edwin de Angel, Earl E. Swartzlander Jr., Jacob A. Abraham: A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic. ICCD 1994: 302-305
92 S. Surya, Pradip Bose, Jacob A. Abraham: Architectural Performance Verification: PowerPCTM Processors. ICCD 1994: 344-347
91 Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell: Verification of Circuits Described in VHDL through Extraction of Design Intent. VLSI Design 1994: 417-420
90EEMarc E. Levitt, Kaushik Roy, Jacob A. Abraham: BiCMOS logic testing. IEEE Trans. VLSI Syst. 2(2): 241-248 (1994)
89EEHoon Chang, Jacob A. Abraham: An efficient critical path tracing algorithm for sequential circuits. Microprocessing and Microprogramming 40(10-12): 913-916 (1994)
1993
88EEHoon Chang, Jacob A. Abraham: VIPER: An Efficient Vigorously Sensitizable Path Extractor. DAC 1993: 112-117
87EENaveena Nagi, Abhijit Chatterjee, Jacob A. Abraham: DRAFTS: Discretized Analog Circuit Fault Simulator. DAC 1993: 509-514
86EEGopi Ganapathy, Jacob A. Abraham: Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor. DAC 1993: 550-555
85 Praveen Vishakantaiah, Jacob A. Abraham: Impact of Behavioral Learning on the Compilation of Sequential Circuit Tests. FTCS 1993: 370-379
84EENaveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham: Fault-based automatic test generator for linear analog circuits. ICCAD 1993: 88-91
83 Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham: MIXER: Mixed-Signal Fault Simulator. ICCD 1993: 568-571
82 Praveen Vishakantaiah, Thomas Thomas, Jacob A. Abraham, Magdy S. Abadir: AMBIANT: Automatic Generation of Behavioral Modifications for Testability. ICCD 1993: 63-66
81 Praveen Vishakantaiah, Jacob A. Abraham, Daniel G. Saab: CHEETA: Composition of Hierarchical Sequential Tests Using ATKET. ITC 1993: 606-615
80 Sankaran Karthik, Jacob A. Abraham, Raymond P. Voith: Optimizations for Behavioral/RTL Simulation. VLSI Design 1993: 311-316
79EERobert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham: Benchmarking Parallel Processing Platforms: An Applications Perspective. IEEE Trans. Parallel Distrib. Syst. 4(8): 947-954 (1993)
78EERobert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham: VLSI logic and fault simulation on general-purpose parallel computers. IEEE Trans. on CAD of Integrated Circuits and Systems 12(3): 446-460 (1993)
77EENaveena Nagi, Abhijit Chatterjee, Jacob A. Abraham: Fault simulation of linear analog circuits. J. Electronic Testing 4(4): 345-360 (1993)
1992
76EEPraveen Vishakantaiah, Jacob A. Abraham, Magdy S. Abadir: Automatic Test Knowledge Extraction from VHDL (ATKET). DAC 1992: 273-278
75 Ghani A. Kanawati, Nasser A. Kanawati, Jacob A. Abraham: FERRARI: A Tool for The Validation of System Dependability Properties. FTCS 1992: 336-344
74 Junsheng Long, W. Kent Fuchs, Jacob A. Abraham: Compiler-Assisted Static Checkpoint Insertion. FTCS 1992: 58-65
73EEDaniel G. Saab, Youssef Saab, Jacob A. Abraham: CRIS: a test cultivation program for sequential VLSI circuits. ICCAD 1992: 216-219
72EERabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu: Automatic test generation for linear digital systems with bi-level search using matrix transform methods. ICCAD 1992: 224-228
71 Sankaran Karthik, Jacob A. Abraham: Distributed VLSI Simulation on a Network of Workstations. ICCD 1992: 508-511
70 John Moondanos, Jacob A. Abraham: Sequential Redundancy Identification Using Verification Techniques. ITC 1992: 197-205
69 Jawahar Jain, Jacob A. Abraham, James R. Bitner, Donald S. Fussell: Probabilistic Verification of Boolean Functions. Formal Methods in System Design 1(1): 61-115 (1992)
68 V. S. S. Nair, Yatin Vasant Hoskote, Jacob A. Abraham: Probabilistic Evaluation of On-Line Checks in Fault-Tolerant Multiprocessor Systems. IEEE Trans. Computers 41(5): 532-541 (1992)
67EEThomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham: Test compaction for sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 11(2): 260-267 (1992)
66EEChun-Hung Chen, Jacob A. Abraham: Generation and evaluation of current and logic tests for switch-level sequential circuits. J. Electronic Testing 3(4): 359-366 (1992)
1991
65 Jawahar Jain, Jim Bitner, Donald S. Fussell, Jacob A. Abraham: Probabilistic Design Verification. ICCAD 1991: 468-471
64 Sankaran Karthik, Indira de Souza, Joseph T. Rahmeh, Jacob A. Abraham: Interlock Schemes for Micropiplines: Application to a Self-Timed Rebound Sorter. ICCD 1991: 393-396
63 Chun-Hung Chen, Jacob A. Abraham: High Quality Tests for Switch-Level Circuits Using Current and Logic Test Generation Algorithms. ITC 1991: 615-622
62 Gopi Ganapathy, Jacob A. Abraham: Hardware Acceleration Alone Will Not Make Fault Grading ULSI a Reality. ITC 1991: 848-857
61 Abhijit Chatterjee, Jacob A. Abraham: Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model. IEEE Trans. Computers 40(10): 1133-1148 (1991)
60EEAbhijit Chatterjee, Jacob A. Abraham: Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling. J. Electronic Testing 2(4): 351-372 (1991)
1990
59EERamachandra P. Kunda, Jacob A. Abraham, Bharat Deep Rathi, Prakash Narain: Speed Up of Test Generation Using High-Level Primitives. DAC 1990: 594-599
58EEDavid T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham: Derivation of signal flow for switch-level simulation. EURO-DAC 1990: 301-305
57EEKaushik Roy, Jacob A. Abraham: High level test generation using data flow descriptions. EURO-DAC 1990: 480-484
56 Chun-Hung Chen, Jacob A. Abraham: Mixed-Level Sequential Test Generation Using a Nine-Valued Relaxation Algorithm. ICCAD 1990: 230-233
55 David Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham: SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. ICCAD 1990: 66-69
54 Junsheng Long, W. Kent Fuchs, Jacob A. Abraham: Forward Recovery Using Checkpointing in Parallel Systems. ICPP (1) 1990: 272-275
53EERobert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham: Design of a scalable parallel switch-level simulator for VLSI. SC 1990: 615-624
52 Abhijit Chatterjee, Jacob A. Abraham: The Testability of Generalized Counters Under Multiple Faulty Cells. IEEE Trans. Computers 39(11): 1378-1385 (1990)
51 V. S. S. Nair, Jacob A. Abraham: Real-Number Codes for Bault-Tolerant Matrix Operations On Processor Arrays. IEEE Trans. Computers 39(4): 426-435 (1990)
50 Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Vijay Balasubramanian, Jacob A. Abraham: Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor. IEEE Trans. Computers 39(9): 1132-1145 (1990)
49EEDaniel G. Saab, Robert B. Mueller-Thuns, David Blaauw, Joseph T. Rahmeh, Jacob A. Abraham: Hierarchical multi-level fault simulation of large systems. J. Electronic Testing 1(2): 139-149 (1990)
1989
48EEDavid Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh: Automatic Generation of Behavioral Models from Switch-Level Descriptions. DAC 1989: 179-184
47EECarol V. Gura, Jacob A. Abraham: Average Interconnection Length and Interconnection Distribution Based on Rent's Rule. DAC 1989: 574-577
46EEKaushik Roy, Jacob A. Abraham: A Novel Approach to Accurate Timing Verification Using RTL Descriptions. DAC 1989: 638-641
45 Jacob A. Abraham: Advances in VLSI-Testing. IFIP Congress 1989: 1013-1018
44 Kurt H. Thearling, Jacob A. Abraham: An Easily Computed Functional Level Testability Measure. ITC 1989: 381-390
43 Marc E. Levitt, Jacob A. Abraham: The Economics of Scan Design. ITC 1989: 869-874
1988
42EECarol V. Gura, Jacob A. Abraham: Improved Methods of Simulating RLC Couple and Uncoupled Transmission Lines Based on the Method of Characteristics. DAC 1988: 300-305
41EEPatrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers: Fault Simulation in a Distributed Environment. DAC 1988: 686-691
40 Jing-Yang Jou, Jacob A. Abraham: Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing. ICPP (1) 1988: 359-362
39 M. J. Marlett, Jacob A. Abraham: DC_IATP : An Iterative Analog Circuit Test Generation Program for Generating DC Single Pattern Tests. ITC 1988: 839-844
38 Jing-Yang Jou, Jacob A. Abraham: Fault-Tolerant FFT Networks. IEEE Trans. Computers 37(5): 548-561 (1988)
1987
37 W. Kent Fuchs, Kun-Lung Wu, Jacob A. Abraham: Comparison and Diagnosis of Large Replicated Files. IEEE Trans. Software Eng. 13(1): 15-22 (1987)
36EEAbhijit Chatterjee, Jacob A. Abraham: On the C-Testability of Generalized Counters. IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 713-726 (1987)
35EEWilliam A. Rogers, John F. Guzolek, Jacob A. Abraham: Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations. IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 848-862 (1987)
1986
34EEHsi-Ching Shih, Jacob A. Abraham: Transistor-level test generation for physical failures in CMOS circuits. DAC 1986: 243-249
33 Chien-Yi Chen, Jacob A. Abraham: On the Design of Fault-Tolerant Systolic Arrays with Linear Cells. FJCC 1986: 400-409
32 Kien A. Hua, Jacob A. Abraham: Design of Systems with Concurrent Error Detection Using Software Redundancy. FJCC 1986: 826-835
31 Jacob A. Abraham: Research in Reliable VLSI Architectures at the University of Illinois. FJCC 1986: 890-893
30 Prithviraj Banerjee, Jacob A. Abraham: A Probabilistic Model of Algorithm-Based Fault Tolerance in Array Processors for Real-Time Systems. IEEE Real-Time Systems Symposium 1986: 72-78
29 Robert H. Fujii, Jacob A. Abraham: Approaches to Circuit Level Design for Testability. ITC 1986: 480-483
28 Hongtao P. Chang, William A. Rogers, Jacob A. Abraham: Structured Functional Level Test Generation Using Binary Decision Diagrams. ITC 1986: 97-104
27 W. Kent Fuchs, Kun-Lung Wu, Jacob A. Abraham: Low-Cost Comparison and Diagnosis of Large Remotely Located Files. Symposium on Reliability in Distributed Software and Database Systems 1986: 67-73
26 Prithviraj Banerjee, Jacob A. Abraham: Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems. IEEE Trans. Computers 35(4): 296-306 (1986)
25 Timothy C. K. Chou, Jacob A. Abraham: Distributed Control of Computer Systems. IEEE Trans. Computers 35(6): 564-567 (1986)
24EEHsi-Ching Shih, Joseph T. Rahmeh, Jacob A. Abraham: FAUST: An MOS Fault Simulator with Timing Information. IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 557-563 (1986)
1985
23EEWilliam A. Rogers, Jacob A. Abraham: High level hierarchical fault simulation techniques. ACM Conference on Computer Science 1985: 89-97
22 Peter Y.-T. Hsu, Joseph T. Rahmeh, Edward S. Davidson, Jacob A. Abraham: TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology. ISCA 1985: 28-35
21 Robert H. Fujii, Jacob A. Abraham: Self-Test for Microprocessors. ITC 1985: 356-361
20 William A. Rogers, Jacob A. Abraham: CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator. ITC 1985: 710-716
19EENiraj K. Jha, Jacob A. Abraham: Design of Testable CMOS Logic Circuits Under Arbitrary Delays. IEEE Trans. on CAD of Integrated Circuits and Systems 4(3): 264-269 (1985)
18EEPrithviraj Banerjee, Jacob A. Abraham: A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 4(3): 312-321 (1985)
1984
17 Prithviraj Banerjee, Jacob A. Abraham: Fault-Secure Algorithms for Multiple-Processor Systems. ISCA 1984: 279-287
16 Ramaswami Dandapani, Janak H. Patel, Jacob A. Abraham: Design of Test Pattern Generators for Built-In Test. ITC 1984: 315-319
15 Dhananjay Brahme, Jacob A. Abraham: Functional Testing of Microprocessors. IEEE Trans. Computers 33(6): 475-485 (1984)
14 Kuang-Hua Huang, Jacob A. Abraham: Algorithm-Based Fault Tolerance for Matrix Operations. IEEE Trans. Computers 33(6): 518-528 (1984)
1983
13 Richard L. Norton, Jacob A. Abraham: Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets ISCA 1983: 277-282
12 W. Kent Fuchs, Jacob A. Abraham, Kuang-Hua Huang: Concurrent Error Detection in VLSI Interconnection Networks ISCA 1983: 309-315
11 Jacob A. Abraham: Incorporating Test Technology into an Undergraduate Curriculum. ITC 1983: 162
10 Prithviraj Banerjee, Jacob A. Abraham: Generating Tests for Physical Failures in MOS Logic Circuits. ITC 1983: 554-559
9 Timothy C. K. Chou, Jacob A. Abraham: Load Redistribution Under Failure in Distributed Systems. IEEE Trans. Computers 32(9): 799-808 (1983)
1982
8 Kuang-Hua Huang, Jacob A. Abraham: Efficient parallel algorithms for processor arrays. ICPP 1982: 268-279
7 Richard L. Norton, Jacob A. Abraham: Using write back cache to improve performance of multi-user multiprocessors. ICPP 1982: 326-331
6 Timothy C. K. Chou, Jacob A. Abraham: Load Balancing in Distributed Systems. IEEE Trans. Software Eng. 8(4): 401-412 (1982)
1981
5 Jacob A. Abraham: Functional Level Test Generation for Complex Digital Systems. ITC 1981: 461-462
4 Jacob A. Abraham, Daniel Gajski: Design of Testable Structures Defined by Simple Loops. IEEE Trans. Computers 30(11): 875-884 (1981)
1980
3 Satish M. Thatte, Jacob A. Abraham: Test Generation for Microprocessors. IEEE Trans. Computers 29(6): 429-441 (1980)
1978
2 Ravindra Nair, Satish M. Thatte, Jacob A. Abraham: Efficient Algorithms for Testing Semiconductor Random-Access Memories. IEEE Trans. Computers 27(6): 572-576 (1978)
1975
1 Jacob A. Abraham: A Combinatorial Solution to the Reliability of Interwoven Redundant Logic Networks. IEEE Trans. Computers 24(5): 578-584 (1975)

Coauthor Index

1Magdy S. Abadir [76] [82] [97] [118] [119] [150] [151] [161] [164] [165] [167] [176] [192] [193] [195]
2Mark Aitken [114]
3Zeyad Alkhalifa [136]
4Edwin de Angel [93]
5Alexandre Ardelea [239]
6Prakash Arunachalam [115] [125]
7Adnan Aziz [124] [241]
8Dave Baker [148]
9Vijay Balasubramanian [50]
10Ashok Balivada [84] [100] [102] [105] [108] [109]
11Prithviraj Banerjee (Prith Banerjee) [10] [17] [18] [26] [30] [50] [55] [107]
12Paul Bassett [240]
13Jason Baumgartner [177]
14Wendy Belluomini [199]
15Jayanta Bhadra [142] [155] [164] [165] [167] [168] [180] [183] [192] [194] [205]
16Stephen Bijansky [241]
17James R. Bitner [69] [97] [101] [118]
18Jim Bitner [65]
19David Blaauw (David T. Blaauw) [48] [49] [55] [58]
20Pradip Bose [92] [153]
21Dhananjay Brahme [15]
22Gary D. Carpenter [210]
23Chia-Lun Chang [207]
24Henry Chang [162]
25Hongtao P. Chang [28]
26Hoon Chang [88] [89] [116]
27Craig M. Chase [125]
28Abhijit Chatterjee [36] [52] [60] [61] [72] [77] [83] [84] [87] [94] [96] [102] [105] [110] [127] [190] [196] [217] [232]
29Chien-Yi Chen [33]
30Chun-Hung Chen [56] [63] [66]
31Jin Chen [108]
32Timothy C. K. Chou [6] [9] [25]
33Chen-chau Chu [148]
34Ji Hwan (Paul) Chun [196] [197] [202] [216]
35Robert F. Damiano [78] [79]
36Ramaswami Dandapani [16]
37Ramyanshu Datta [198] [199] [204] [210] [217] [231] [232]
38Edward S. Davidson [22]
39Bulent I. Dervisoglu [98]
40Sujit Dey [132]
41Abdulkadir Utku Diril [217] [232]
42Steve Dollens [162]
43Qingqi Dou [214] [219] [234]
44Patrick A. Duba [41]
45E. Allen Emerson [206] [220]
46Zhenhai Fu [222]
47W. Kent Fuchs [12] [27] [37] [54] [74]
48Robert H. Fujii [21] [29]
49Masahiro Fujita [112] [135] [145] [166]
50Donald S. Fussell [65] [69] [91] [97] [101] [104] [112] [117] [118] [135] [145] [166]
51Daniel Gajski (Daniel D. Gajski) [4]
52Rajesh Galivanche [243]
53Jianhua Gan [189] [201]
54Gopi Ganapathy [62] [86] [111]
55Vijay K. Garg [194]
56Sergey Gavrilov [238]
57Gregorio Gervasio [148]
58Ranjit Gharpurey [227] [236]
59Karl-Erwin Großpietsch [133]
60Ravi Gupta [198] [231]
61Carol V. Gura [42] [47]
62Sankar Gurumurthy [228] [245] [247]
63John F. Guzolek [35]
64H. Hao [119]
65Yatin Vasant Hoskote [68] [91] [100] [103] [104] [113] [117] [128]
66Peter Y.-T. Hsu [22]
67Guanghui Hu [148]
68Kien A. Hua [32]
69Kuang-Hua Huang [8] [12] [14]
70Warren A. Hunt Jr. [218]
71C. Hunter [119]
72Tony Hurson [148]
73Sungbae Hwang [170] [179] [182] [184]
74Jawahar Jain [65] [69] [97] [101] [112] [118] [135] [145] [166]
75Abhijit Jas [243]
76Rathish Jayabharathi [110] [120] [138]
77Kamalnayan Jayaraman [172]
78Niraj K. Jha [19]
79Jing-Yang Jou [38] [40]
80Vijay Kiran Kalyanam [229]
81Ghani A. Kanawati [75] [99]
82Nasser A. Kanawati [75] [99]
83S. Karako [193]
84Sankaran Karthik [64] [71] [80] [114]
85Nash Khouzam [235]
86Byoungho Kim [209] [216] [222] [235]
87Kyoil Kim [183]
88Martin Kinkade [148]
89Fatih Kocan [173]
90Hans-Dieter Kochs [133]
91A. Kolhatkar [195]
92Arun Krishnamachary [147] [163] [174] [178] [186]
93Narayanan Krishnamurthy [136] [150] [151] [161] [167] [192]
94Jente B. Kuang [199]
95Andreas Kuehlmann [177]
96Ramachandra P. Kunda [59]
97Sandip Kundu [98]
98Parag K. Lala [187]
99Kyung Tek Lee [120] [129] [139]
100Songjun Lee [157]
101Marc E. Levitt [43] [90] [98]
102Chia-Pin R. Liu [144]
103Junsheng Long [54] [58] [74]
104Johannes Maier [133]
105M. J. Marlett [39]
106Andrew K. Martin [150] [151] [161] [165] [205]
107Glidden Martin [114]
108Chandler McDowell [199]
109Amit Mittal [248]
110Baker Mohammad [240] [241]
111Robert K. Montoye [199]
112John Moondanos [70] [91] [117]
113Dinos Moundanos [101] [103] [113] [128] [130] [134] [143]
114Robert B. Mueller-Thuns [48] [49] [53] [55] [78] [79]
115Rajarshi Mukherjee [112] [135] [145] [166]
116Naveena Nagi [77] [83] [84] [87] [94] [102] [105] [127]
117Ravindra Nair [2]
118Suku Nair (V. S. S. Nair) [50] [51] [68] [107] [136]
119Prakash Narain [59]
120Sani R. Nassif [229] [244]
121Suriyaprakash Natarajan [245]
122Lucie Nechanicka [238]
123Wayne M. Needham [119]
124Hung C. Ngo [199]
125Thomas M. Niermann [67]
126Clay Nordquist [129]
127Richard L. Norton [7] [13]
128Kevin J. Nowka [199] [210] [217] [232]
129Michael Orshansky [229]
130Jen-Chieh Ou [230]
131Rajendran Panda [238] [239] [248]
132Pankaj Pant [110]
133Srinivasu Pappula [114]
134Joonsung Park [226] [233]
135Janak H. Patel [16] [67] [72] [98]
136Srinivas Patil [243]
137Qiang Qiang [207] [208] [211] [230]
138Ashwin Raghunathan [190] [196] [204]
139Joseph T. Rahmeh [22] [24] [48] [49] [50] [64]
140Richard Raimi [146]
141Bharat Deep Rathi [59]
142Michel Renovell [133]
143Gordon Roberts [162]
144William A. Rogers [20] [23] [28] [35] [41]
145Jeongjin Roh [140] [152] [154] [158] [181]
146Don E. Ross [101]
147Kaushik Roy [46] [50] [57] [90]
148Rabindra K. Roy [41] [67] [72]
149Daniel G. Saab [48] [49] [53] [55] [58] [73] [78] [79] [81] [95] [106] [156] [171] [173] [185] [207] [208] [211] [223] [228] [230]
150Youssef Saab [73] [95] [106]
151Avijit Saha [159]
152Martin Saint-Laurent [240]
153Sriram Sambamurthy [212] [237] [247]
154Nina Saxena [159]
155Antony Sebastine [198] [204] [231]
156Alper Sen [194]
157Suresh Seshadri [158] [160]
158Jian Shen [124] [126] [131] [137] [148] [149]
159Hsi-Ching Shih [24] [34]
160Hongjoong Shin [190] [197] [203] [209] [216] [226] [233]
161Roman Solovyev [238]
162Mani Soma [162]
163Indira de Souza [64]
164Bob Stettler [114]
165Charles E. Stroud [162]
166Craig B. Stunkel [50]
167Hector R. Sucar [98]
168Robert W. Sumners (Rob Sumners) [123] [142] [155] [221]
169Savithri Sundareswaran [225] [238] [239] [248]
170S. Surya [92]
171Earl E. Swartzlander Jr. [93] [188]
172Koichiro Takayama [135] [145] [166]
173Rajeshwary Tayade [225] [229] [244]
174Satish M. Thatte [2] [3]
175Kurt H. Thearling [44]
176Thomas Thomas [82]
177Whitney J. Townsend [187] [188] [191]
178Jiajin Tu [213]
179Raghuram S. Tupuri [121] [122] [147] [156] [163] [174] [180] [212] [237]
180G. Vandling [193] [195]
181Shobha Vasudevan [200] [206] [213] [220] [221] [224] [246]
182Vivekananda M. Vedula [168] [171] [172] [175] [180] [185] [191]
183Ramtilak Vemu [215] [228] [243] [245] [247]
184Praveen Vishakantaiah [76] [81] [82] [85] [114]
185Vinod Viswanath [213] [218] [221] [224] [246]
186Raymond P. Voith [80]
187Ron G. Walther [98] [119]
188Li-C. Wang [193] [195]
189Kun-Lung Wu [27] [37]
190Shouli Yan [189] [201]
191Heebyung Yoon [127]
192Hak-soo Yu [157] [169] [184] [197] [202] [203]
193Jun Yuan [124]
194Jing Zeng [164] [176] [193] [195]
195Chaoming Zhang [227] [236]
196Yun Zhang [248]
197Hong Zheng [105]
198Hong Helena Zheng [109]
199Yervant Zorian [132]
200Manuel A. d'Abreu [72] [98] [114] [115] [138] [198] [231]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)