17. VLSI Design 2004: Mumbai, India

@proceedings{DBLP:conf/vlsid/2004,
  title     = {17th  International Conference on VLSI Design (VLSI Design 2004),
               with the 3rd International Conference on Embedded Systems Design,
               5-9 January 2004, Mumbai, India},
  booktitle = {VLSI Design},
  publisher = {IEEE Computer Society},
  year      = {2004},
  isbn      = {0-7695-2072-3},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Tutorials

• Samar Saha, Bhaskar Gadepally:
  Technology CAD: Technology Modeling, Device Design and Simulation. 3-5
  
• Susmita Sur-Kolay, Parthasarathi Dasgupta, Bhargab B. Bhattacharya, Sujit T. Zachariah:
  Physical Design Trends and Layout-Based Fault Modeling. 6-8
  
• Indradeep Ghosh, Rajarshi Mukherjee, Mukul R. Prasad, Masahiro Fujita:
  High Level Design Validation: Current Practices and Future Directions. 9-11
  
• Krithi Ramamritham, Kavi Arya, Gerhard Fohler:
  System Software for Embedded Applications. 12-14
  
• Siva Narendra, Vasantha Erraguntla, James Tschanz, Nitin Borkar:
  Design Challenges in Sub-100nm High Performance Microprocessors. 15-17
  
• Peter A. Beerel, Jordi Cortadella, Alex Kondratyev:
  Bridging the Gap between Asynchronous Design and Designers. 18-20
  
• Janusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer, Thomas Rinderknecht:
  Embedded Test for Low Cost Manufacturing. 21-23
  
• Gérard Berry:
  Synchronous Methodology for Designing Hardware, Software and Mixed Embedded Systems. 24-
  

Plenary Talks

• P. Jespers:
  High Speed Integrated A to D Converters. 29
  
• Hiroshi Iwai:
  CMOS Scaling for sub-90 nm to sub-10 nm. 30-
  

Voltage Analog Design

• Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín:
  Techniques for very low-voltage operation of continuous-time analog CMOS circuits. 39-
  

• Srinjoy Mitra, A. N. Chandorkar:
  Design of Amplifier with Rail-to-Rail CMR with 1V Power Supply. 52-56
  
• S. V. Gopalaiah, A. P. Shivaprasad, Sukanta K. Panigrahi:
  Design of Low Voltage Low Power CMOS OP-AMPS with Rail-to-Rail Input/Output Swing. 57-
  

Low Power Logic Synthesis

• Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy:
  Modeling and Estimation of Leakage in Sub-90nm Devices. 65-
  

• Maitrali Marik, Ajit Pal:
  Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs. 73-78
  
• D. Satyanarayana, Santanu Chattopadhyay, Jakki Sasidhar:
  Low Power Combinational Circuit Synthesis targeting Multiplexer based FPGAs. 79-84
  
• Debasis Samanta, Ajit Pal:
  Synthesis of Low Power High Performance Dual-VT PTL Circuits. 85-
  

Formal Verification

• Masahiro Fujita:
  Formal Verification of C Language Based VLSI Designs. 93-
  

• Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti:
  Formal Verification of Modules under Real Time Environment Constraints. 103-108
  
• Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan:
  Property Refinement Techniques for Enhancing Coverage of Formal Property Verification. 109-114
  
• Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham:
  Towards The Complete Elimination of Gate/Switch Level Simulations. 115-
  

Embedded System Design

• Sujay Phadke, Rhishikesh Limaye, Siddharth Verma, Kavitha Subramanian:
  On Design and Implementation of an Embedded Automatic Speech Recognition System. 127-132
  
• Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf:
  Embedded Hardware Face Detection. 133-
  

Mixed Signal Design

• Jaijeet S. Roychowdhury:
  Algorithmic Macromodelling Methods for Mixed-Signal Systems. 141-
  

• Hao San, Haruo Kobayashi, Shinya Kawakami, Nobuyuki Kuroiwa:
  An Element Rotation Algorithm for Multi-bit DAC Nonlinearities in Complex Bandpass \Delta\SigmaAD Modulators. 151-156
  
• Anup Savla, Jennifer Leonard, Arun Ravindran:
  Error Correction In Pipelined ADCS Using Arbitrary Radix Calibration. 157-162
  
• Rasoul Dehghani:
  A 2.5GHz CMOS Fully-Integrated \Delta\Sigma-Controlled Fractional-N Frequency Synthesizer. 163-167
  
• Nitin Bansal, Amit Katyal:
  A Switch-Cap Regulator for SoC Applications. 168-
  

Design Methodology

• Ronald W. Mehler, Dian Zhou:
  Automated Architectural Optimization of Digital FIR Filters. 177-182
  
• Rui Min, Zhiyong Xu, Yiming Hu, Wen-Ben Jone:
  Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs. 183-188
  
• Vijay D'Silva, S. Ramesh, Arcot Sowmya:
  Bridge Over Troubled Wrappers: Automated Interface Synthesis. 189-194
  
• Ashok K. Murugavel, N. Ranganathan:
  Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. 195-200
  
• Seok-Soo Yoon, Seok-Ryong Yoon, Seon Wook Kim, Chulwoo Kim:
  Charge-Sharing-Problem Reduced Split-Path Domino Logic. 201-
  

Leakage Reduction

• Rohini Krishnan, José Pineda de Gyvez:
  Low Energy Switch Block For FPGAs. 209-214
  
• Sergey Romanovsky, Arun Achyuthan, Sreedhar Natarajan, Wing Leung:
  Leakage Reduction techniques in a 0.13um SRAM Cell. 215-221
  
• Ge Yang, Zhongda Wang, Sung-Mo Kang:
  Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies. 222-227
  
• Narender Hanchate, Nagarajan Ranganathan:
  A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. 228-233
  
• Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown:
  Analysis and Optimization of Enhanced MTCMOS Scheme. 234-239
  
• Kaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj:
  Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. 240-
  

Embedded OS and Software

• Victor Yodaiken:
  New frontiers for embedded computing. 249-
  

• Krishnan Srinivasan, Karam S. Chatha:
  An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures. 255-260
  
• Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
  Energy-Optimizing Source Code Transformations for OS-driven Embedded Software. 261-266
  
• Weidong Wang, Anand Raghunathan, Niraj K. Jha:
  Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization. 267-
  

VLSI Technology

• Cor Claeys:
  Technological Challenges of Advanced CMOS Processing and Their Impact on Design Aspects. 275-
  

• H. C. Srinivasaiah, Navakanta Bhat:
  Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment. 285-290
  
• Purushothaman Srinivasan, B. Vootukuru, Durga Misra:
  Screening of Hot Electron Effect During Plasma Processing. 291-
  

Reconfigurable Design

• Satnam Singh:
  Designing Reconfigurable Systems in Lava. 299-306
  
• Krishna Sekar, Kanishka Lahiri, Sujit Dey:
  Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips. 307-
  

Design Tools

• Kausik Datta, P. P. Das:
  Assertion Based Verification Using HDVL. 319-
  

• Tun Li, Yang Guo, Sikun Li:
  Design and Implementation of a Parallel Verilog Simulator: PVSim. 329-334
  
• Raghukiran Sreeramaneni, Sarma B. K. Vrudhula:
  Energy Profiler for Hardware/Software Co-Design. 335-
  

Emerging Areas in VLSI

• Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
  A Tuturial on the Emerging Nanotechnology Devices. 343-360
  
• David D. Wentzloff, Benton H. Calhoun, Rex Min, Alice Wang, Nathan Ickes, Anantha Chandrakasan:
  Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes. 361-
  

• Bill Witowsky:
  A Vision for the Broadband Network. 373-
  

• Dennis Monticelli:
  A System Approach to Energy Management. 377
  
• Phil Moorby:
  Design for Verification with SystemVerilog. 378-
  

RF Design

• Sanjive Agarwala, Paul Wiley, Arjun Rajagopal, Anthony M. Hill, Raguram Damodaran, Lewis Nardini, Tim Anderson, Steven Mullinnix, Jose Flores, Heping Yue, Abhijeet Chachad, John Apostol, Kyle Castille, Usha Narasimha, Tod Wolf, N. S. Nagaraj, Manjeri Krishnan, Luong Nguyen, Todd Kroeger, Mike Gill, Peter Groves, Bill Webster, Joel Graber, Christine Karlovich:
  A 800 MHz System-on-Chip for Wireless Infrastructure Applications. 381-
  

• Jie Long, Robert J. Weber:
  A Low Voltage, Low Noise CMOS RF Receiver Front-End. 393-397
  
• V. Veeresh Babu, Sumantra Seth, A. N. Chandorkar:
  Design of RF Tuner for Cable Modem Applications. 398-403
  
• Amlan Ghosh, Bevin G. Perumana, Ashudeb Dutta, Padmanava Sen, Yogesh Kumar, Vipul Garg, T. K. Bhattacharyya, Nirmal B. Chakrabarti:
  Design and Implementation of 935 MHz FM Transceiver for Radio Telemetry and 2.45 GHz Direct AQPSK Transmitter in CMOS. 404-409
  
• Padmanava Sen, Vipul Garg, Ramesh Garg, Nirmal B. Chakrabarti:
  Design of Power Amplifiers at 2.4 GHz/900 MHz and Implementation of On-chip Linearization Technique in 0.18/0.25 ?I`m CMOS. 410-415
  
• T. Hui Teo, Ee-Sze Khoo, Dasgupta Uday, Chin-Boon Tear:
  Design, Analysis, and Implementation of Analog Complex Filter for Low-IF Wireless LAN Application. 416-
  

Interconnect

• N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara:
  Interconnect Modeling for Copper/Low-k Technologies. 425-
  

• Puneet Gupta, Andrew B. Kahng:
  Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling. 431-436
  
• Marong Phadoongsidhi, Kewal K. Saluja:
  Static Timing Analysis of Irreversible Crosstalk Noise Pulse Faults. 437-442
  
• P. Subrahmanya, R. Manimegalai, V. Kamakoti, Madhu Mutyam:
  A Bus Encoding Technique for Power and Cross-talk Minimization. 443-448
  
• Suvodeep Gupta, Srinivas Katkoori:
  Intra-Bus Crosstalk Estimation Using Word-Level Statistics. 449-454
  
• Vani Prasad, Madhav P. Desai:
  On Buffering Schemes for Long Multi-Layer Nets. 455-
  

Fault Detection

• Salvador Mir, Libor Rufer, Bernard Courtois:
  On-chip testing of embedded transducers. 463-
  

• Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Enamul Amyeen:
  Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults. 475-480
  
• Manan Syal, Michael S. Hsiao:
  Untestable Fault Identification using Recurrence Relations and Impossible Value Assignments. 481-486
  
• Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
  Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults. 487-492
  
• Josh Yang, Baosheng Wang, André Ivanov:
  Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode. 493-498
  
• Pan Zhongliang:
  Neural Network Model for Testing Stuck-at and Delay Faults in Digital Circuit. 499-
  

System on Chip

• Mahesh Mehendale:
  Challenges in the Design of Embedded Real-time DSP SoCs. 507-511
  
• C. P. Ravikumar:
  Multiprocessor Architectures for Embedded System-on-chip Applications. 512-519
  
• Ramalingam Sridhar:
  System-on-Chip (SoC): Clocking and Synchronization Issues. 520-
  

• P. R. Suresh, P. K. Sundararajan, Anshuli Goel, H. Udayakumar, C. Srinivasan, Vasudev Sinari, Raghavendrakumar Ravinutala:
  Package-silicon co-design - Experiment with an SOC design. 531-
  

Analog Design

• Qadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri:
  A tunable gm-C filter with low variation across Process, Voltage and Temperature. 539-544
  
• K. Narasimhulu, Siva Narendra, V. Ramgopal Rao:
  The Influence of Process Variations on the Halo MOSFETs and its Implications on the Analog Circuit performance. 545-550
  
• S. S. Prasad, Pradip Mandal:
  A CMOS Beta Multiplier Voltage Reference with Improved Temperature Performance and Silicon Tunability. 551-
  

Design Methodology

• Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma:
  Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework. 559-564
  
• G. Hazari, Madhav P. Desai, A. Gupta, S. Chakraborty:
  A Novel Technique Towards Eliminating the Global Clock in VLSI Circuits. 565-570
  
• Aditya Mittal, Madhav P. Desai:
  A Distributed and Pipelined Controller for a Modular and Scalable Hardware Emulator. 571-
  
• Jens Bieger, Sorin A. Huss, Michael Jung, Stephan Klaus, Thomas Steininger:
  Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach. 577-
  

Test Pattern Generation

• Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain:
  Can SAT be used to Improve Sequential ATPG Methods? 585-
  
• Vivekananda M. Vedula, Whitney J. Townsend, Jacob A. Abraham:
  Program Slicing for ATPG-Based Property Checking. 591-596
  
• Aman Kokrady, C. P. Ravikumar:
  Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures. 597-
  

Embedded Systems

• Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar:
  Tamper Resistance Mechanisms for Secure, Embedded Systems. 605-
  

Poster Session A

• R. Dehghani, Seyed Mojtaba Atarodi, B. Bornoosh, Ali Afzali-Kusha:
  A Reduced Complexity 3rd Order Digital Delta-Sigma Modulator for Fractional-N Frequency Synthesis. 615-618
  
• S. Nagar, Baquer Mazhari:
  A New Approach To Topology Selection For Cell-Level Analog Circuits. 619-622
  
• Gagandeep S. Sandha, Pawan K. Singh, C. Pradeep Kumar, D. Nagchoudhuri:
  Quantitative Model for Thermal Behaviour of an Analog Integrated Circuit. 623-626
  
• Ghanshyam Nayak, P. R. Mukund:
  Chip Package Co-Design of a Heterogeneously Integrated 2.45GHz CMOS VCO using Embedded Passives in a Silicon Package. 627-630
  
• M. Benmansour, P. R. Mukund:
  A Tuned Wideband LNA in 0.25?I`m IBM Process For RF Communication Applications. 631-634
  
• Tejasvi Das, P. R. Mukund:
  A Low Noise Current-mode Readout circuit for CMOS Image Sensing Applications. 635-638
  
• F. Farbiz, M. Farazian, M. Emadi, K. Sadeghi:
  Sizing Consideration for Leakage Control Transistor. 639-641
  
• Sukumar Jairam, C. Venkatesh, Navakanta Bhat, Shyam Singh, Rudra Pratap:
  A Quasi Static Model for a Simply Supported Beam in a Circuit Simulation Framework. 642-645
  
• Shrutin Ulman:
  Analytical Expressions For Static Characteristics of Submicron CMOS Inverters. 646-649
  
• Venkat Rao, Gaurav Singhal, Anshul Kumar:
  Real Time Dynamic Voltage Scaling For Embedded Systems. 650-653
  
• M. DeRenzo, Mary Jane Irwin, Narayanan Vijaykrishnan:
  Designing Leakage Aware Multipliers. 654-657
  
• Dainius Ciuplys, Per Larsson-Edefors:
  On Maximum Current Estimation in CMOS Digital Circuits. 658-661
  
• Anurag Chaudhry, M. Jagadesh Kumar:
  Exploring the Novel Characteristics of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET using Two-Dimensional Numerical Simulation Studies. 662-665
  
• Ashis Kumar Mal, Anindya Sundar Dhar:
  Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors. 666-669
  
• Ashok K. Murugavel, N. Ranganathan:
  Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis. 670-
  

Poster Session B

• N. Sudha:
  An ASIC Implementation of Kohonen's Map Based Color Image Compression. 677-680
  
• Chih-Jen Yen, Wen-Yaw Chung, Mely Chen Chi:
  A Compact Low-Power Buffer Amplifier with Dynamic Bias Control Technique. 681-684
  
• Madhu Mutyam:
  Preventing Crosstalk Delay using Fibonacci Representation. 685-688
  
• N. Sudha:
  An Area-Efficient Pipelined Array Architecture for Euclidean Distance Transformation and Its FPGA Implementation. 689-692
  
• Mikael Millberg, Erland Nilsson, Rikard Thid, Shashi Kumar, Axel Jantsch:
  The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip. 693-696
  
• Manvendra Singh, B. S. Chauhan, N. K. Sharma:
  VLSI Architecture of Centroid Tracking Algorithms for Video Tracker. 697-700
  
• Pradip Mandal:
  A Narrow Pulse- Suppressing Filter For Input Buffer. 701-704
  
• Sachin Shrivastava, Dhanoop Varghese, Vikas Narang, N. V. Arvind:
  Improved Approach for Noise Propagation to Identify Functional Noise Violations. 705-708
  
• Sreeram Chandrasekar, Sachin Shrivastava, Ajoy Mandal, Sornavalli Ramanathan:
  An Efficient Approach to Crosstalk Noise Analysis at Multiple Operating Modes. 709-712
  
• Stelian Alupoaei, Srinivas Katkoori:
  Energy Model Based Macrocell Placement for Wirelength Minimization. 713-716
  
• Jeremy Chan, Sri Parameswaran:
  NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture. 717-720
  
• Rajeev Murgai:
  Net Buffering in the Presence of Multiple Timing Views. 721-726
  
• N. V. Arvind, K. A. Rajagopal, H. S. Ajith, Das Suparna:
  Path Based Approach for Crosstalk Delay Analysis. 727-730
  
• Varun Jindal, Alpana Agarwal:
  Carry Circuitry for LUT-Based FPGA. 731-734
  
• Minoru Watanabe, Fuminori Kobayashi:
  An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation. 735-
  

Poster Session C

• Irith Pomeranz, Sudhakar M. Reddy:
  On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression. 741-744
  
• Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi:
  ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis. 745-748
  
• Syed Saif Abrar:
  Cycle-Accurate Energy Model and Source-Independent Characterization Methodology for Embedded Processors. 749-752
  
• Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar:
  Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories. 753-756
  
• Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Syed Mostahed Ali Chowdhury, Ahsan Raja Chowdhury:
  Synthesis of Full-Adder Circuit Using Reversible Logic. 757-760
  
• Sourabh Saluja, Anshul Kumar:
  Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture. 761-764
  
• Nilesh Modi, Jordi Cortadella:
  Boolean Decomposition Using Two-literal Divisors. 765-768
  
• Nirav Patel, M. Srihari, Pooja Maheswari, G. N. Nandakumar:
  An Efficient Method to Generate Test Vectors for Combinational Cell Verification. 769-772
  
• Ravi Saini, Pramod Tanwar, A. S. Mandal, S. C. Bose, Raj Singh, Chandra Shekhar:
  Design of an Application Specific Instruction Set Processor for Parametric Speech Synthesis. 773-775
  
• Gurashish Singh Brar, Susmit Biswas, Sudipta Kundu, Arijit Mukhopadhyay, Pratik Worah, Anupam Basu:
  OaSis: An Application Specific Operating System for an Embedded Environment. 776-779
  
• Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan:
  Synthesis of Application Specific Multiprocessor Architectures for Process Networks. 780-783
  
• Rajat Arora, Michael S. Hsiao:
  Enhancing SAT-based Bounded Model Checking using Sequential Logic Implications. 784-787
  
• Subrangshu Das, Subash G. Chandar, Ashutosh Tiwari:
  Reset Careabouts in a SoC Design. 788-
  

Plenary Talk

• Raman Srinivas:
  Building Giga-Transistor [Enterprise] Microprocessors. 801-
  

Device Physics

• M. K. Radhakrishnan:
  Device Reliability and Failure Mechanisms Related to Gate Dielectrics and Interconnects. 805-808
  
• Harald Gossner:
  ESD protection for the deep sub micron regime - a challenge for design methodology. 809-
  

Papers

• Tushar S. Shelar, G. S. Visweswaran:
  Inclusion of Thermal Effects in the Simulation of Bipolar Circuits using Circuit Level Behavioral Modeling. 821-826
  
• M. Jagadesh Kumar, Vinod Parihar:
  A New Surface Accumulation Layer Transistor(SALTran) Concept for Current Gain Enhancement in Bipolar Transistors. 827-831
  
• Rajiv V. Joshi, K. Kroell, Ching-Te Chuang:
  A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI. 832-
  

Routing and Interconnect

• Sachin S. Sapatnekar:
  High-Performance Power Grids For Nanometer Technologies. 839-844
  
• Jörg Henkel, Wayne Wolf, Srimat T. Chakradhar:
  On-chip networks: A scalable, communication-centric embedded system design paradigm. 845-
  

Papers

• Gary William Grewal, Thomas Charles Wilson, Ming Xu, Dilip K. Banerji:
  Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees. 855-862
  
• Sumit D. Mediratta, Jeff Sondeen, Jeffrey T. Draper:
  An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System. 863-868
  
• PariVallal Kannan, Dinesh Bhatia:
  Estimating Pre-Placement FPGA Interconnection Requirements. 869-
  

Testing

• Rajat Gupta:
  Digital Design: The components of a new paradigm. 877-
  

Papers

• Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara:
  Random Access Scan: A solution to test power, test data volume and test time. 883-888
  
• Sagar S. Sabade, D. M. H. Walker:
  Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests. 889-894
  
• Xiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee:
  At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. 895-900
  
• M. S. Gaur, Mark Zwolinski:
  Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique. 901-906
  
• Gethin Norman, David Parker, Marta Z. Kwiatkowska, Sandeep K. Shukla:
  Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking. 907-
  

Processor Architecture

• Chandra Shekhar, Raj Singh, A. S. Mandal, S. C. Bose, Ravi Saini, Pramod Tanwar:
  Application Specific Instruction Set Processors: Redefining Hardware-Software Boundary. 915-
  

• Prabhat Mishra, Arun Kejariwal, Nikil Dutt:
  Synthesis-driven Exploration of Pipelined Embedded Processors. 921-926
  
• S. Chakraverty:
  Cosynthesis of multiprocessor architectures with high availability. 927-932
  
• Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
  Instruction-Based Delay Fault Self-Testing of Processor Cores. 933-
  

UWB RF

• Ramesh Harjani, Jackson Harvey, Robert Sainati:
  Analog/RF Physical Layer Issues For UWB Systems. 941-
  

Design Contest

• Arijit Mukhopadhyay, Saptarshi Biswas, Pratik Worah, Ramasish Das, Susmit Biswas, Anupam Basu:
  Katha-Mala: A Voice Output Communication Aid for the Children with Severe Speech and Multiple Disorders (SSMI). 951-
  

• Amit Gupta, Steven P. Levitan, Leo Selavo, Donald M. Chiarulli:
  High-Speed Optoelectronics Receivers in SiGe. 957-
  

Layout and Placement

• Stelian Alupoaei, Srinivas Katkoori:
  Ant Colony Optimization Technique for Macrocell Overlap Removal. 963-968
  
• Yan Feng, Dinesh P. Mehta:
  Constrained Floorplanning with Whitespace. 969-974
  
• Kun Gao, Dinesh P. Mehta:
  Floorplan Classification Algorithms. 975-980
  
• Pranav Anbalagan, Jeffrey A. Davis:
  Maximum Multiplicity Distributions for Length Prediction Driven Placement. 981-
  

Noise Analysis

• Shabbir H. Batterywala, Narendra V. Shenoy:
  Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables. 989-994
  
• Rohan Mandrekar, Madhavan Swaminathan, Sungjun Chun:
  Application of Wavelets and Generalized Pencil-Of-Function Method for the Extraction of Noise Current Spectrum and Simulation of Simultaneous Switching Noise. 995-1000
  
• Li Ding, Pinaki Mazumder:
  Dynamic Noise Margin: Definitions and Model. 1001-
  

Analog and RF Test

• Richard McCartney, Nikhil Balram:
  Advanced LCD Timing Controller IC with Memory-Assisted Response Time Compensation. 1009-
  

• Sasikumar Cherubal, Ramakrishna Voorakaranam, Abhijit Chatterjee, John Mclaughlin, Jason L. Smith, David M. Majernik:
  Concurrent RF Test Using Optimized Modulated RF Stimuli. 1017-1022
  
• Antonija Soldo, Anand Gopalan, P. R. Mukund, Martin Margala:
  A Current Sensor for On-Chip, Non-Intrusive Testing of RF Systems. 1023-1026
  
• Sunil Rafeeque, Vinita Vasudevan:
  A Built-in-Self-Test Scheme for Digital to Analog Converters. 1027-
  

Low Power Design

• Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
  CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. 1035-1040
  
• Lin Zhong, Niraj K. Jha:
  Dynamic Power Optimization of Interactive Systems. 1041-1047
  
• Nikolaus Voß, Bärbel Mertsching:
  A Framework for Low Power Audio Design. 1048-
  

H/W Impl. of Algorithms

• T. K. Priya, K. Sridharan:
  An Efficient Algorithm to Construct Reduced Visibility Graph and Its FPGA Implementation. 1057-1062
  
• Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa:
  VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design. 1063-
  

Motion Estimation

• Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, V. Bala Kuteshwar:
  A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation. 1071-1076
  
• J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf:
  An Architecture for Motion Estimation in the Transform Domain. 1077-1082
  
• Aleksandar Beric, Ramanathan Sethuraman, Harm Peters, Jef L. van Meerbergen, Gerard de Haan, Carlos A. Alba Pinto:
  A 27 mW 1.1 mm2 Motion Estimator for Picture-Rate Up-converter. 1083-