3. IWSOC 2003: Calgary, Alberta, Canada

• Message from the General Chairs.
  
• Program Committee.
  

SoC Design Methodologies 1

• Yuanqing Guo, Gerard J. M. Smit, Hajo Broersma, Paul M. Heysters:
  Template Generation and Selection Algorithms. 2-6
  
• Sérgio G. Araújo, Antônio C. Mesquita, Aloysio Pedroza:
  Optimized Datapath Design by Evolutionary Computation. 6-9
  
• Matthias Grünewald, Jörg-Christian Niemann, Ulrich Rückert:
  A performance evaluation method for optimizing embedded applications. 10-15
  
• Kuo-Hsing Cheng, Wei-Chun Chang, Chia Ming Tu:
  A Robust Handshake for Asynchronous System. 16-19
  

SoC Physical Design - Invited

• Bill Halpin, Naresh Sehgal, C. Y. Roger Chen:
  Detailed Placement with Net Length Constraints. 22-27
  
• Laleh Behjat, Anthony Vannelli:
  Steiner Tree Construction Based on Congestion for the Global Routing Problem. 28-31
  
• Dorothy Kucar, Anthony Vannelli:
  InterconnectionModelling Using Distributed RLC Models. 32-35
  

Low Power SoCs

• Patricia Guitton-Ouhamou, Cécile Belleudy, Michel Auguin:
  Energy Optimization in a HW/SW Tool: Design of Low. 38-43
  
• Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya, Prasanna Venkatesh Kannan:
  Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design. 44-47
  
• Li-Chuan Weng, Xiaojun Wang, Bin Liu:
  A Survey of Dynamic Power Optimization Techniques. 48-52
  
• T. W. Fox, A. Carreira, L. E. Turner:
  The Design of Low-Power Fixed-Point FIR Differentiator IP Blocks. 53-58
  

Arithmetic Techniques

• Amr T. Abdel-Hamid, Sofiène Tahar, El Mostapha Aboulhamid:
  IP Watermarking Techniques: Survey and Comparison. 60-65
  
• Minyi Fu, Graham A. Jullien, Vassil S. Dimitrov, Majid Ahmadi, William C. Miller:
  The Application of 2D Algebraic Integer Encoding to a DCT IP Core. 66-69
  
• Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman:
  Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic. 70-75
  
• Nitish Patel, George Coghill, Sing Kiong Nguang:
  Digital Realization of Analogue Computing Elements Using Bit Streams. 76-80
  

Analog and Mixed Signals 1

• S. M. Rezaul Hasan:
  A High Performance Wide-band CMOS Transimpedance Amplifier for Optical Transceivers. 82-85
  
• Jhy-Neng Yang, Yi-Chang Cheng, Chen-Yi Lee:
  A Design of CMOS Broadband Amplifier With High-Q Active Inductor. 86-89
  
• Kuo-Hsing Cheng, Yu-lung Lo, Wen Fang Yu, Shu-Yin Hung:
  A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation. 90-93
  
• Sau-Mou Wu, Ron-Yi Liu, Wei-Liang Chen:
  A 5.8-GHz High Efficient, Low Power, Low Phase Noise CMOS VCO for IEEE 802.11a. 94-97
  
• Stephen Machan:
  A Low-Power Fully Differential 2.4-GHz Prescaler in 0.18µm CMOS Technology. 98-100
  

Reconfigurable Hardware

• Peter Waldeck, Neil W. Bergmann:
  Dynamic Hardware-Software Partitioning on Reconfigurable System-on-Chip. 102-105
  
• Philippe Brunet, Camel Tanougast, Yves Berviller, Serge Weber:
  Hardware Partitioning Software for Dynamically Reconfigurable SoC Design. 106-111
  
• Neil W. Bergmann, Peter Waldeck, John A. Williams:
  A Catalog of Hardware Acceleration Techniques for Real-Time Reconfigurable System on Chip. 112-115
  
• Magesh Sadasivam, Sangjin Hong:
  Application Specific Coarse-Grained FPGA for Processing Element in Real-Time Parallel Particle Filters. 116-119
  
• Costantino Giaconia, Antonio Di Stefano, Giuseppe Capponi:
  Reconfigurable Digital Instrumentation Based on FPGA. 120-122
  
• H. Emam, M. A. Ashour, H. Fekry, A. M. Wahdan:
  Introducing an FPGA based - genetic algorithms in the applications of blind signals separation. 123-127
  

Digital Circuits

• Shih-Chang Hsia:
  A High Speed Multi -Input Comparator with Clocking-Charge Based for Low-Power Systems. 130-133
  
• Dae-Ik Kim, Myung-Whan An, Ho-Yong Chung, Suk-Young Kim:
  Area Efficient Implementation of Noise Generation System. 134-137
  
• Panduka Wijetunga:
  High-performance crossbar design for system-on-chip. 138-143
  
• Mountassar Maamoun, Abdelhalim Benbelkacem, Daoud Berkani, Abderrezak Guessoum:
  Interfacing in Microprocessor-based Systems with a Fast Physical Addressing. 144-149
  

SoC Applications 1

• Hiroto Saito, Shogo Nakamura, Masahide Yoneyama:
  A Speech Speed Control Using Fourier Composite Approach. 152-156
  
• Andrew Y. Lin, Karl S. Gugel, José Carlos Príncipe:
  Feasibility of Fixed-Point Transversal Adaptive Filters in FPGA Devices with Embedded DSP Blocks. 157-160
  
• Sergio Saponara, Luca Fanucci, L. Serafini:
  Low-Power FFT/IFFT VLSI Macro Cell for Scalable Broadband VDSL Modem. 161-166
  
• Shih-Chang Hsia:
  VLSI Implementation of Very Low-Power Motion Estimator for Scaleable Coding Systems. 167-170
  

Modeling Issues in SoCs

• Mohamed Karray, Patricia Desgreys, Jean-Jacques Charlot:
  A CMOS inverter TIA modeling with VHDL-AMS. 172-174
  
• Armando Armaroli, Marcello Coppola, Mario Diaz-Nava, Luca Fanucci:
  High Level Modeling and Simulation of a VDSL Modem in SystemC 2.0 - IPsim. 175-180
  
• Sherif G. Aly, Ashraf M. Salem:
  Java Based Co-Verification of Expedited Mobile Device. 181-184
  
• Kasim A. Rashid:
  Multi-Models Adaptive Controller for Multivariable Systems. 185-189
  

Embedded Processors

• Jari Heikkinen, Tommi Rantanen, Andrea G. M. Cilio, Jarmo Takala, Henk Corporaal:
  Evaluating Template-Based Instruction Compression on Transport Triggered Architectures. 192-195
  
• J. L. Silva, R. M. Costa, G. H. R. Jorge:
  RtrASSoc - An Adaptable Superscalar Reconfigurable System-On-Chip. 196-200
  
• James Northern III, Michael A. Shanblatt:
  An Evolutionary Approach to Configuring an Embedded System Based on Power Consumption. 201-204
  
• Oswaldo Cadenas, Graham M. Megson:
  Pullpipelining: A technique for systolic pipelined circuits. 205-210
  

SoC Design Methodologies 2

• Ali Habibi, Sofiène Tahar:
  A Survey oA Survey on System-On-a-Chip Designn System-On-a-Chip Design. 212-215
  
• Azeddien M. Sllame:
  Design Space Exploration Methodology for High-Performance System-on-a-Chip Hardware Cores. 216-221
  
• Christian Panis, Raimund Leitner, Jari Nurmi:
  Scaleable Shadow Stack for a Configurable DSP Concept. 222-227
  
• S. Regimbal, Jean-Francois Lemire, Yvon Savaria, Guy Bois, El Mostapha Aboulhamid, A. Baron:
  Automating Functional Coverage Analysis Based on an Executable Specification. 228-234
  

Sensors

• Aldo Romani, Fabio Campi, S. Ronconi, Marco Tartagni, Gianni Medoro, Nicolò Manaresi:
  A System-on-a-Programmable-Chip for Real-Time Control of Massively Parallel Arrays of Biosensors and Actuators. 236-241
  
• Vojko Matko:
  Porosity Sensor by Using Quartz Crystals and Two Excitation Signals. 242-246
  
• Abdallah Kassem, J. Wang, Abdelhakim Khouas, Mohamad Sawan, Mounir Boukadoum:
  Pipelined Sampled-Delay Focusing CMOS Implementation for Ultrasonic Digital Beamforming. 247-250
  
• José Vicente Calvano, Marcelo Lubaszewski:
  Designing for Test Analog Signal Processors for MEMS-Based Inertial Sensors. 251-256
  

Analog and Mixed Signals 2

• Bogdan Georgescu, Joshua K. Nakaska, Robert G. Randall, James W. Haslett:
  A 0.28µm CMOS Bluetooth Frequency Synthesizer for Integration with a Bluetooth SOC Reference Platform. 258-263
  
• Lin Jia, Alper Cabuk, Jianguo Ma, Kiat Seng Yeo:
  A 52 GHz VCO with Low Phase Noise Implemented in SiGe BiCMOS Technology. 264-269
  
• Rodrigo L. Oliveira Pinto, Franco Maloberti:
  Novel Design Methodology for Short-Channel MOSFET Analog Circuits. 270-276
  
• Franz Schlögl, Horst Zimmermann:
  120nm CMOS Operational Amplifier with Pseudo-Cascodes and Positive Feedback. 277-280
  
• Suchitav Khadanga:
  Synchronous programmable divider design for PLL Using 0.18 um cmos technology. 281-286
  
• Tao Lin, Zhou Zhengou:
  The Implementation of 100MHz Data Acquisition Based on FPGA. 287-291
  

Interconnect

• Chung-Seok (Andy) Seo, Abhijit Chatterjee:
  Free-Space Optical Interconnect for High-Performance MCM Systems. 294-298
  
• Neal K. Bambha, Shuvra S. Bhattacharyya, Gary Euliss:
  Design Considerations for Optically Connected Systems on Chip. 299-303
  
• Partha Pratim Pande, Cristian Grecu, André Ivanov:
  High-Throughput Switch-Based Interconnect for Future SoCs. 304-310
  
• Chang Hee Pyoun, Chi-Ho Lin, Hi-Seok Kim, Jong Wha Chong:
  The Efficient Bus Arbitration Scheme in SoC Environment. 311-315
  
• John Ferguson:
  The Glue in a Confident SoC Flow. 316-319
  
• Masud H. Chowdhury, Yehea I. Ismail:
  Analysis of Coupling Noise in Dynamic Circuit. 320-325
  

Memory Techniques for SoCs

• Mohammed Sayed, Wael M. Badawy:
  A New Class of Computational RAM Architectures for Real-Time MPEG-4 Applications. 328-332
  
• Mehboob Alam, Choudhury A. Rahman, Wael M. Badawy, Graham A. Jullien:
  Efficient Distributed Arithmetic Based DWT Architecture for Multimedia Applications. 333-336
  
• Chia-Tien Dan Lo:
  The Design of a Self-Maintained Memory Module for Real-Time Systems. 337-342
  
• Jae Hong Park, Jung-Min Choi, Min Ho Kim, Jong Wha Chong:
  An Efficient Equalizer Architecture Using Tap Allocation Memory for HDTV Channel. 343-349
  

SoC Medical Applications

• Aman A. Al-Imari, Kasim A. Rashid, Mohammed Al-Dagstany:
  Telemetry Based System for Measurement and Monitoring of Biomedical Signals. 352-356
  
• Aman A. Al-Imari, Kasim A. Rashid, Najat Hader Al-Egaidy:
  Design and Implementation of a Surface Electromycogram System for Sport Field Application. 357-361
  
• J. R. Keilman, Graham A. Jullien, Karan V. I. S. Kaler:
  A SoC Bio-analysis Platform for Real-time Biological Cell Analysis-on-a-Chip. 362-368
  

SoC Testing

• Jiann-Chyi Rau, Yi-Yuan Chang, Chia-Hung Lin:
  An Efficient Mechanism for Debugging RTL Description. 370-373
  
• Jiann-Chyi Rau, Kuo-Chun Kuo:
  An Enhanced Tree-Structured Scan Chain for Pseudo-Exhaustive Testing of VLSI Circuits. 374-377
  
• Emil Dumitrescu, Dominique Borrione:
  Symbolic Simulation as a Simplifying Strategy for SoC Verification. 378-383
  

SoC Applications 2

• Nikzad Babaii Rizvandi, Abdolreza Nabavi:
  Design, Simulation and Implementation of a Low-Power Digital Decimation Filter for G.232 Standard. 390-393
  
• Fernando De Bernardinis, Luca Fanucci, T. Ramacciotti, Pierangelo Terreni:
  A QoS Internet Protocol Scheduler on the IXP1200 Network Platform. 394-399
  
• Robert Gulde, Michael Weeks:
  A Position Control System Design. 400-405