ITC 1995:
Washington,
DC,
USA
Proceedings IEEE International Test Conference 1995, Driving Down the Cost of Test, Washington, DC, USA, October 21-25, 1995.
IEEE Computer Society 1995, ISBN 0-7803-2992-9 
@proceedings{DBLP:conf/itc/1995,
title = {Proceedings IEEE International Test Conference 1995, Driving
Down the Cost of Test, Washington, DC, USA, October 21-25, 1995},
publisher = {IEEE Computer Society},
year = {1995},
isbn = {0-7803-2992-9},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Session 1:
Plenary
Keynote Address
Invited Address
- Philippe Chauveau:
Design and Testing of the On-Ramps to the Information Superhighway.
11
Session 2:
RAM BIST and Intelligent Testing
Session 3:
New Test Considerations for Mixed-Signal Devices
Session 4: Quality, I-DDQ, and the DUT Interface
Session 5:
Delay Testing
Session 6:
Microprocessor Test
- Graham Hetherington, Greg Sutton, Kenneth M. Butler, Theo J. Powell:
Test Generation and Design for Test for a Large Multiprocessing DSP.
149-156
- Marc E. Levitt, Srinivas Nori, Sridhar Narayanan, G. P. Grewal, Lynn Youngs, Anjali Jones, Greg Billus, Siva Paramanandam:
Testability, Debuggability, and Manufacturability Features of the UltraSPARCTM-I Microprocessor.
157-166
- Jen-Tien Yen, Marie Sullivan, Carlos Montemayor, Pete Wilson, Richard Evers:
Overview of PowerPCTM 620 Multiprocessor Verification Strategy.
167-174
- Hong Hao, Rick Avra:
Structured Design-for-Debug - The SuperSPARCTM II Methodology and Implementation.
175-183
Session 7:
MCM Test Methods
Session 8:
Test SPC and Support Systems
Session 9:
Test Generation and Fault Simulation
Session 10 - Panel:
Designers are from Venus,
Test Engineers are from Mars
Session 11 - Panel:
Is High-Level Test Synthesis just DFT?
Session 12 - Panel:
Test Challenges of Contract Manufacturing
Session 13 - Panel:
Why is Mixed-Signal Testing Such a Mess Anyway?
Session 14 - Panel:
Test Quality:
Stuck-at Fault,
PPM Rejects or?
- Keith Baker:
Stuck-at Faults, PPMs Rejects or? What doe the SIA Roadmaps Say?
299
- John M. Acken:
The Final Barriers to Widespread Use of IDDQ Testing.
300
- Ron Wantuck:
Test Quality: Required Stuck-at Fault Coverage with the Use of IDDQ Testing.
301
Session 15:
Design for Testability - I
Session 16:
IC Test Issues
- A. Frisch, Mitch Aigner, T. Almy, Hans J. Greub, M. Hazra, S. Mohr, Nicholas J. Naclerio, W. Russell, M. Stebniskey:
Supplying Known-Good Die for MCM Applications Using Low-Cost Embedded Testing.
328-335
- V. Ramakrishnan, D. M. H. Walker:
IC Performance Prediction System.
336-344
- Fabian Vargas, Michael Nicolaidis, Yervant Zorian:
An Approach for Designing Total-Dose Tolerant MCMs Based on Current Monitoring.
345-354
Session 17:
New Test Techniques for Mixed-Signal Devices
Session 18:
Microprocessor-Related Topics
Session 19:
Design for Testability - II
Session 20:
Applications of Test Cost Analysis
Session 21:
High-Speed ATE Architectures and Timing
Session 22:
Defect Detection and Diagnosis
Session 23:
Performance-Driven BIST Insertion
Session 24:
IC-Defect Detection:
Advancements in Design,
Test and Analysis Methods
Session 25:
Uniformity and Flexibility:
Capatalizing on Boundary-Scan's Assets
Session 26:
Test at the Functional Level
Session 27:
IC Testing and Diagnosis
Session 28:
Topics in Test Techniques
Session 29 - Case Studies:
Successful Experiences with MCM Test
- Andrew Flint:
Using the Right Tools and Techniques leads to Successful Testing of MCMs.
673
Session 30:
Synthesis for Testability
Session 31:
Software Testing
Session 32 - Case Studies:
Test Synthesis
Session 33:
Unconventional Test Development
Session 34:
Systems and Testing:
Practical Applications and Costs
Session 35:
BIST Pattern Generation and Compaction
Session 36:
Design and Simulations Topics
- Carol Pyron, W. C. Bruce:
Implementing 1149.1 in the PowerPCTM RISC Microprocessor Family.
844-850
- Lee Whetsel:
Improved Boundary Scan Design.
851-860
- Kamal K. Varma:
Compiled Code, Dynamic Worst Case Timing Simulation Tracking Multiple Causality.
861-869
Session 37:
Changing the Test Paradigm:
ATE and Board Test Systems
Session 38:
IC Current-Test Techniques,
Production Results,
and Quality Improvement Methods
Session 39 - Panel:
Highlights of the MCM Test Workshop
- Alan W. Righter:
Solving Known Good Die (and Substrate) Test Issues.
916
- David C. Keezer:
Electrical Troubleshooting, Diagnostics, and Repair of Multichip Modules.
917
Session 40 - Panel:
What New Test Standards Do We Need?
Session 41 - Panel:
Bringing Down the Cost of Test... The ATE Way?... The DFT Way?... The Boundary Scan Way?... The I-DDQ Way?... Or What?
Session 42 - Panel:
What's so Different about Deep-Submicron Test?
ITC Lecture Series:
Unpowered "Opens" Testing
- Kenneth P. Parker, David Greene:
The ITC Lecture Series: An Experiment.
925
- Jack Ferguson:
Finding I/O Faults on In-Circuit ICs Using Parasitic Transistor Tests.
926
- Joe Wrinn:
Two New Techniques for Identifying Opens on Printed Circuit Boards: Analog Junction Test & Radio Frequency Induction Test.
927
- Ted T. Turner:
Capacitive Leadframe Testing.
928
Session T1:
Telecom Test:
The Future is Here!
Session T2:
Design-For-Test Strategies for Novel Telecommunications Test Problems
Session T3:
Test Technology and Strategy Challenges Facing Telecom Manufacturing Test
Session T4:
Telecom Systems:
Are We Getting What We Wanted?
Copyright © Mon Nov 2 20:54:08 2009
by Michael Ley (ley@uni-trier.de)
