ITC 1993:
Baltimore,
MD,
USA
Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics - Join Them, Baltimore, Maryland, USA, October 17-21, 1993.
IEEE Computer Society 1993, ISBN 0-7803-1430-1 
@proceedings{DBLP:conf/itc/1993,
title = {Proceedings IEEE International Test Conference 1993, Designing,
Testing, and Diagnostics - Join Them, Baltimore, Maryland, USA,
October 17-21, 1993},
publisher = {IEEE Computer Society},
year = {1993},
isbn = {0-7803-1430-1},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Plenary
System Testing
I-DDQ And Logic Testing of CMOS Bridging
SPC-Based Intelligent Test
Advancement In Test Generation
- Tom Austin:
Creating A Mixed-Signal Simulation Capability for Concurrent IC Design and Test Program Development.
125-132
- Tony Taylor:
Tools and Techniques for Converting Simulation Models into Test Patterns.
133-138
- Ravindranath Naiknaware, G. N. Nandakumar, Srinivasa Rao Kasa:
Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation.
139-148
- Jan Moorman, Steven D. Millman:
Visualizing Test Information: A Novel Approach for Improving Testability.
149-156
IEEE STD 1149.1 In Action
Software Testability
Cost-Effective Application Of Ate
Delay Testing - Self Test
Panel:
IEEE STD 1149.1:
Barriers - Real and Irrational!
Panel:
Known Good Die:
A Key To Cost Effective MCMs
Panel:
DFT - Profit Or Loss?
Panel:
Software Testing Got You Down?
How Can CMOS IC Quality Be Improved?
- Hong Hao, Edward J. McCluskey:
Very-Low-Voltage Testing for Weak CMOS Logic ICs.
275-284
- Rick Gayle:
The Cost of Quality: Reducing ASIC Defects with IDDQ At-Speed Testing and Increased Fault Coverage.
285-292
- Paul C. Wiscombe:
A Comparison of Stuck-At Fault Coverage and IDDQ Testing on Defect Levels.
293-299
Testability Structures For Mixed-Signal Board Testing
On-Product Bist
Multichip Module Testing
DFT:
Putting Principles Into Practice
Making Test Generation Faster
Test Engineering Strategies I
Test Data Management
- Jim Mosley III:
A Flexible Approach to Data Collection for Component Test Systems.
461-470
- John O'Donnell:
Generated in Real-time Instant Process Statistics ("GRIPS"): Immediate, Tester-computed Test Statistics, Eliminating the Post-processing of Datalogs.
471-477
- Paresh Gondalia, Allan Gutjahr, Wen-Ben Jone:
Realizing a High Measure of Confidence for Defect Level Analysis of Random Testing.
478-487
DFT:
Winning It With Partial Scan
IEEE STD 1149.1 Design Issues
Timing Systems - Analysis And Time Measurement
- Richard K. Feldman:
A Novel Instrument for Accurate Time Measurement in Automatic Calibration of Test Systems.
544-551
- Arnold Frisch, Thomas Almy:
Timing Analyzer for Embedded Testing.
552-555
- Will Creek:
Characterization of Edge Placement Accuracy in High-Speed Digital Pin Electronics.
556-565
Realistic Quality Practices
Panel:
Mixed-Signal Test Bus:
Has It Arrived?
Panel:
Test Synthesis:
Fact Or Fiction?
Panel:
Fault Coverage Numbers:
What Do They Really Mean?
Constrained Test Generation
Novel And Practical Power Supply Current Test Techniques
Board Test:
Analog,
Bare Board,
Digital
Mixed Signal Device Test Techniques
Compact Delay Testing
Synthesis And Testability
Microprocessor And VLSI Testing Case Studies
Design-For-Test Considerations For Mixed-Signal Devices
- Eiichi Teraoka, Toru Kengaku, Ikuo Yasui, Kazuyuki Ishikawa, Takahiro Matsuo, Hideyuki Wakada, Narumi Sakashita, Yukihiko Shimazu, Takeshi Tokuda:
A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC.
791-796
- Ed Flaherty, Andrew Allen, John Morris:
Design for Testability of a Modular, Mixed Signal Family of VLSI Devices.
797-804
- M. F. Toner, Gordon W. Roberts:
A BIST Scheme for an SNR Test of a Sigma-Delta ADC.
805-814
Memory Test
Software Testing Methods
Detection Of Physical Defects
Test Engineering Strategies II
Selected Topics In Test
- Paul Sakamoto, Tom Chiu:
High-Speed Sampling Capability for a VLSI Mixed-Signal Tester.
918-927
- Kent Kwang, Hsin Wang, Arthur Hu, Mitsuyuki Asaki, Hironobu Niijima:
CAD-Driven High-Precision E-Beam Positioning.
928-935
- Richard F. Herlein:
Terminating Transmission lines in the Test Environment.
936-944
- R. Mehtani, B. Atzema, M. De Jonghe, Richard Morren, Geert Seuren, Taco Zwemstra:
Mix Test: A Mixed-Signal Extension to a Digital Test System.
945-953
Delay Testing
DFT:
New Tricks Of The Old Trade
BIST Pattern Generation
1992 Best Paper
- Robert C. Aitken:
BP-1992 A Comparison of Defect Models for Fault Location with IDDQ Measurements.
1051-1060
Copyright © Mon Nov 2 20:54:07 2009
by Michael Ley (ley@uni-trier.de)
