38. ISMVL 2008: Dallas, Texas, USA

• Thomas W. Williams:
  EDA to the Rescue of the Silicon Roadmap. 1
  
• Mark H. Nodine, Craig M. Files:
  A Mature Methodology for Implementing Multi-Valued Logic in Silicon. 2-7
  
• Hirokatsu Shirahama, Takahiro Hanyu:
  Design of High-Performance Quaternary Adders Based on Output-Generator Sharing. 8-13
  
• Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu:
  Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices. 14-19
  
• Yasushi Yuminaka, Yasunori Takahashi:
  Time-Domain Pre-Emphasis Techniques for Equalization of Multiple-Valued Data. 20-25
  
• Dan A. Simovici:
  Betweenness, Metrics and Entropies in Lattices. 26-31
  
• Hajime Machida, Jovanka Pantovic:
  On Maximal Hyperclones on {0, 1} — A New Approach. 32-37
  
• Hajime Machida, Tamas Waldhauser:
  Majority and Other Polynomials in Minimal Clones. 38-43
  
• Doina Logofatu, Rolf Drechsler:
  Comparative Study by Solving the Test Compaction Problem. 44-49
  
• Shinobu Nagayama, Tsutomu Sasao:
  Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators. 50-56
  
• Tsutomu Sasao:
  On the Complexity of Classification Functions. 57-63
  
• Craig M. Files, Mark H. Nodine:
  MDD with Added Null-Value and All-Value Edges. 64-69
  
• Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu:
  High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. 70-75
  
• Claudio Moraga:
  Permutations under Spectral Transforms. 76-81
  
• Claudio Moraga, Suzana Stojkovic, Radomir S. Stankovic:
  On Fixed Points and Cycles in the Reed Muller Domain. 82-87
  
• Hosam A. Aleem, Ferda Mavituna, David H. Green:
  A Galois Field Approach to Modelling Gene Expression Regulation. 88-93
  
• Stephan Eggersglüß, Rolf Drechsler:
  On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults. 94-99
  
• Victor Chepoi, Nadia Creignou, Miki Hermann, Gernot Salzer:
  Deciding the Satisfiability of Propositional Formulas in Finitely-Valued Signed Logics. 100-105
  
• Josep Argelich, Alba Cabiscol, Inês Lynce, Felip Manyà:
  Encoding Max-CSP into Partial Max-SAT. 106-111
  
• Yuki Watanabe, Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
  High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language. 112-117
  
• Masahiro Miyakawa, Maurice Pouzet, Ivo G. Rosenberg, Hisayuki Tatsumi:
  Semirigid Equivalence Relations on a Finite Set. 118-123
  
• David W. Matula:
  Foundations of Higher Radix Numeric Computation. 124
  
• Mozammel H. A. Khan, Nafisa K. Siddika, Marek A. Perkowski:
  Minimization of Quaternary Galois Field Sum of Products Expression for Multi-Output Quaternary Logic Function Using Quaternary Galois Field Decision Diagram. 125-130
  
• Andrea Masini, Luca Viganò, Margherita Zorzi:
  A Qualitative Modal Representation of Quantum Register Transformations. 131-137
  
• David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller:
  On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams. 138-143
  
• David J. Rosenbaum, Marek A. Perkowski:
  Superposed Quantum State Initialization Using Disjoint Prime Implicants (SQUID). 144-149
  
• Saoussen Bel Hadj Kacem, Amel Borgi, Khaled Ghédira:
  Generalized Modus Ponens Based on Linguistic Modifiers in a Symbolic Multi-Valued Framework. 150-155
  
• Raul Cruz-Cano, Igor N. Aizenberg:
  Soft Computing Methods for Prediction of Replication Origins in Caudoviruses. 156-162
  
• Daniel Stamate:
  Default Reasoning with Imperfect Information in Multivalued Logics. 163-168
  
• Bogdan J. Falkowski, Cheng Fu:
  Classification of Fastest Quaternary Linearly Independent Arithmetic Transforms. 169-173
  
• Kazuki Akutagawa, Kazuya Machida, Takao Waho:
  A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter. 174-179
  
• Nobuaki Okada, Michitaka Kameyama:
  Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells. 180-185
  
• John A. Chandy, Faquir C. Jain:
  Multiple Valued Logic Using 3-State Quantum Dot Gate FETs. 186-190
  
• Martin Lukac, Marek A. Perkowski:
  Projective Measurement-Based Logic Synthesis of Quantum Circuits. 191-196
  
• Theodore W. Manikas, Dale Teeters:
  Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells. 197-201
  
• Mitchell A. Thornton, David W. Matula, Laura Spenner, D. Michael Miller:
  Quantum Logic Implementation of Unary Arithmetic Operations. 202-207
  
• Mozammel H. A. Khan:
  Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits. 208-213
  
• Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler:
  Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. 214-219
  
• Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler:
  RevLib: An Online Resource for Reversible Functions and Reversible Circuits. 220-225
  
• Cicilia C. Lozano, Bogdan J. Falkowski, Tadeusz Luba:
  Properties and Computational Algorithm for Fastest Quaternary Linearly Independent Transforms. 226-231
  
• Susanna Minasyan, Jaakko Astola, Karen O. Egiazarian, Radomir S. Stankovic:
  Hybrid Reed-Muller Haar Transform and its Application in Reduction the Spectral Representations of Logic Functions. 232-237
  
• Radomir S. Stankovic, Jaakko Astola:
  Remarks on Bandwidth and Regularities in Functions on Finite Non-Abelian Groups. 238-243