31. ISMVL 2001:
Warsaw,
Poland
31st IEEE International Symposium on Multiple-Valued Logic (ISMVL 2001),
22-24 May,
2001,
Warsaw,
Poland,
Proceedings. IEEE Computer Society,
2001,
ISBN 0-7695-1083-3
Invited Address
Circuits I
Design and Verification of Systems
Invited Address
Circuits II
Fuzzy Logics and Their Applications I
Circuits III
- Tetsuya Uemura, Toshio Baba:
A Three-Valued D-Flip-Flop and Shift Register Using Multiple-Junction Surface Tunnel Transistors.
89-93
- Takao Waho, Kazufumi Hattori, Y. Takamatsu:
Flash Analog-to-Digital Converter Using Resonant-Tunneling Multiple-Valued Circuits.
94-99
- H. Teng, R. Bolton:
The Use of Arithmetic Operators in a Self-Restored Current-Mode CMOS Multiple-Valued Logic Design Architecture.
100-
Fuzzy Logics and Their Applications II
Invited Address
Tutorial
Invited Address
Logic Design I
Automated Reasoning and Complexity I
Logic Design II
Automated Reasoning and Complexity II
Invited Address
- Takahiro Hanyu:
Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI.
241-
Computing Paradigms
MV Logics and Algebras I
Tutorial
- Arnon Avron:
Classical Gentzen-Type Methods in Propositional Many-Valued Logics.
287-
Decision Diagrams
Fuzzy Logics and Set Theories
Neural Networks
MV Logics and Algebras II
Copyright © Mon Nov 2 20:53:11 2009
by Michael Ley (ley@uni-trier.de)
