ISCAS 2002: Scottsdale, Arizona, USA - Volume 5

• J. B. Miller, John C. McEachen, H. H. Loomis Jr., Michael A. Tope, D. B. Copeland:
  An analysis of noise in timing-based communications over local area networks. 1-4
  
• Xiaojun Wu, Qinye Yin, Hong Zhang:
  Lower-complexity direct symbol detector for multiuser MC-CDMA system using antenna array without vector channel estimation. 5-8
  
• R. Katti, V. V. Bapeswara Rao:
  An array based technique for routing messages in distributed double loop networks. 9-12
  
• Yu-Nan Lin, David W. Lin:
  Analysis of hardlimiting parallel interference cancellation (PIC) for synchronous CDMA communication. 13-16
  
• A. Laitinen, Marko Hännikäinen, Timo Hämäläinen:
  Using SDL a tool for system simulations. 17-20
  
• W. Pietrenko, W. Janke, A. K. Kazimierczuk:
  Large-signal time-domain simulation of class-E amplifier. 21-24
  
• Unni Narayanan, Ki-Seok Chung, Taewhan Kim:
  Enhanced bus invert encodings for low-power. 25-28
  
• I. Hattori, A. Kamo, T. Watanabe, H. Asai:
  Optimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD method. 29-32
  
• A. N. Rudiakova, J. V. Rassokhina, Marian K. Kazimierczuk, V. G. Krizhanovski:
  High-efficiency microwave BJT power amplifier simulation. 33-36
  
• Ernesto Chiarantoni, Girolamo Fornarelli, Silvano Vergura:
  A new method for efficient time-domain simulation of power electronic circuits. 37-40
  
• Robert M. Fox, Inchang Seo, H. Yeo, O. Jeon:
  Leveraged current mirror op amp. 41-44
  
• Ahmed Emira, Edgar Sánchez-Sinencio, M. Schneider:
  Design tradeoffs of CMOS current mirrors using one-equation for all-region model. 45-48
  
• Xuguang Zhang, Ezz I. El-Masry:
  A high-performance, low-voltage, body-driven CMOS current mirror. 49-52
  
• Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang:
  A low-voltage high-speed BiCMOS current switch with enhanced-spectral performance. 53-56
  
• Worapong Tangsrirat, Nobuo Fujii, Wanlop Surakampontorn:
  Current-mode leapfrog ladder filters using CDBAs. 57-60
  
• Marcia G. Méndez-Rivera, José Silva-Martínez, Edgar Sánchez-Sinencio:
  On-chip spectrum analyzer for built-in testing analog ICs. 61-64
  
• Jaime Ramírez-Angulo, C. Lackey, Alejandro Díaz-Sánchez:
  Compact continuous-time analog rank-order filter implementation in CMOS technology. 65-68
  
• Andrea Xotta, Daniele Vogrig, Andrea Gerosa, Andrea Neviani, Alexandre Graell i Amat, Guido Montorsi, M. Bruccoleri, G. Betti:
  An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels. 69-72
  
• J. T. Marienborg, Tor Sverre Lande, Mats Erling Høvin:
  Neuromorphic noise shaping in coupled neuron populations. 73-76
  
• T. M. Massengill, D. M. Wilson, Paul E. Hasler, David W. Graham:
  Empirical comparison of analog and digital auditory preprocessing for automatic speech recognition. 77-80
  
• Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long:
  Static timing analysis based circuit-limited-yield estimation. 81-84
  
• Francky Leyn, Erik Lauwers, Martin Vogels, Georges G. E. Gielen, Willy M. C. Sansen:
  Regression criteria and their application in different modeling cases. 85-8
  
• Massimo Conti, Paolo Crippa, Simone Orcioni, M. Pesare, Claudio Turchetti, Loris Vendrame, S. Lucherini:
  A new methodology for the statistical analysis of VLSI CMOS circuits and its application to flash memories. 89-92
  
• Ángel Rodríguez-Vázquez, Gustavo Liñán, Servando Espejo-Meana, Rafael Domínguez-Castro:
  Mismatch-induced tradeoffs and scalability of mixed-signal vision chips. 93-96
  
• Yu Lin, Randall L. Geiger:
  Resistors layout for enhancing yield of R-2R DACs. 97-100
  
• Bill Pontikakis, Mohamed Nekili:
  A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications. 101-104
  
• Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija:
  Comparative analysis of double-edge versus single-edge triggered clocked storage elements. 105-108
  
• Mohammad M. Mansour, Naresh R. Shanbhag:
  Simplified current and delay models for deep submicron CMOS digital circuits. 109-112
  
• Mohab Anis, Mohamed I. Elmasry:
  Self-timed MOS current mode logic for digital applications. 113-116
  
• Harri Lampinen, Olli Vainio:
  Current-sensing completion detection method for standard cell based digital system design. 117-120
  
• Yew-San Lee, Cheng-Mou Yu, Hung-Kuo Wei, Yen-Hsu Shih, Chen-Yi Lee:
  A novel DCT-based bit plane error resilient entropy coding scheme and codec for wireless image communication. 121-124
  
• Sang-hee Lee, Myungjin Kim, Keun-Bae Kim:
  Modular and efficient architecture for H.263 video codec VLSI. 125-128
  
• Lingfeng Li, Danian Gong, Yun He:
  A single-chip real-time programmable video signal processor. 129-132
  
• Yun-Tai Hsiao, Hung-Der Lin, Kun-Bin Lee, Chein-Wei Jen:
  High-speed memory-saving architecture for the embedded block coding in JPEG2000. 133-136
  
• M. Yagi, T. Shibata:
  An associative-processor-based mixed signal system for robust grayscale image recognition. 137-140
  
• Pedro Amaral, João Goes, Nuno F. Paulino, Adolfo Steiger-Garção:
  An improved low-voltage low-power CMOS comparator to be used in high-speed pipeline ADCs. 141-144
  
• A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
  SRAM oriented memory sense amplifier design in 0.18 /spl mu/m CMOS technology. 145-148
  
• G. A. Al-Rawi:
  A new offset measurement and cancellation technique for dynamic latches. 149-152
  
• Roman Genov, Gert Cauwenberghs:
  Charge-based MOS correlated double sampling comparator and folding circuit. 153-156
  
• Lauri Sumanen, Mikko Waltari, Väinö Hakkarainen, Kari Halonen:
  CMOS dynamic comparators for pipeline A/D converters. 157-160
  
• Aleksandar Tasic, Wouter A. Serdijn:
  Concept of phase-noise tuning of bipolar voltage-controlled oscillators. 161-164
  
• P. Kallam, Edgar Sánchez-Sinencio, Aydin I. Karsilayan:
  An improved Q-tuning scheme and a fully symmetric OTA. 165-168
  
• Bo Shi, Weiyun Shan, Pietro Andreani:
  A 57-dB image band rejection CMOS G/sub m/-C polyphase filter with automatic frequency tuning for Bluetooth. 169-172
  
• Mingdeng Chen, J. Silva-Martinez, S. Rokhsaz, M. Robinson:
  A 1.8V CMOS, 80-200MHz continuous-time 4th order 0.05/spl deg/ equiripple linear phase filter with automatic tuning system. 173-176
  
• Aydin I. Karsilayan, Sung-Ling Huang, Jader A. De Lima:
  Automatic tuning of linearly tunable high-Q filters. 177-180
  
• F. Silveira, D. Flandre:
  A 110 nA pacemaker sensing channel in CMOS on silicon-on-insulator. 181-184
  
• V. S. L. Cheung, H. Luong, Mansun Chan:
  A 0.9-V 0.2-/spl mu/W CMOS single-opamp-based switched-opamp /spl Sigma//spl Delta/ modulator for pacemaker applications. 185-188
  
• Christopher D. Salthouse, Rahul Sarpeshkar:
  A micropower band-pass filter for use in bionic ears. 189-192
  
• Robert Rieger, John Taylor, Nick Donaldson:
  Low noise preamplifier design for nerve cuff electrode recording systems. 193-196
  
• Reid R. Harrison:
  A low-power, low-noise CMOS amplifier for neural recording applications. 197-200
  
• R. Murali, Lihui Wang, Blanca Austin, James D. Meindl:
  Low-power circuit advantages of the scaled accumulation FET. 201-204
  
• L.-E. Wernersson, E. Lind, P. Lindstrom, Pietro Andreani:
  Circuits and devices with integrated VFETs and RTDs. 205-208
  
• Shin-ichi O'uchi, Minoru Fujishima, Koichiro Hoh:
  An 8-qubit quantum-circuit processor. 209-212
  
• Luigi Fortuna, Mattia Frasca, Alessandro Rizzo:
  Self-organising behavior of arrays of nonidentical Josephson junctions. 213-216
  
• Koray Karahaliloglu, Sina Balkir:
  Image processing with quantum dot nanostructures. 217-220
  
• M. Lee, R. B. Anna, Jui-Chu Lee, Scott M. Parker, Kim M. Newton:
  A scalable BSIM3v3 RF model for multi-finger NMOSFETs with ring substrate contact. 221-224
  
• Jaijeet S. Roychowdhury:
  Theory and algorithms for RF sensitivity computation. 225-228
  
• Jian-Yi Wu, Steven B. Bibyk:
  Robust design with virtual tests of mixed-signal circuits in VHDL-AMS. 229-232
  
• Yoondong Park, Steve H. Jen, Bing J. Sheu, Heesook Yoon, In Gyeom Kim:
  An efficient parameter extraction method using statistical optimization in S-CMOS deep-submicron/nanometer model. 233-236
  
• D. Ozis, Kartikeya Mayaram, Terri S. Fiez:
  An efficient modeling approach for substrate noise coupling analysis. 237-240
  
• A. C.-W. Yu, Oscar C. Au, Bing Zeng:
  Removing of blocking artefacts using error-compensation interpolation and fast adaptive spatial-varying filtering. 241-244
  
• Jiho Park, Dong-Chul Park, Robert J. Marks II, Mohamed A. El-Sharkawi:
  Block loss recovery in DCT image encoding using POCS. 245-248
  
• John E. Kleider, Glen P. Abousleman:
  Image quality optimization using computationally efficient variable QoS multicarrier bit-allocation. 249-252
  
• P. Carrai, Ingrid Heynderickx, Paolo Gastaldo, Rodolfo Zunino:
  Image quality assessment by using neural networks. 253-256
  
• Ken-Chung Ho:
  Non-causal error diffusion for image halftoning. 257-260
  
• K. Nandhasri, Jitkasem Ngarmnil, K. Moolpho:
  A 2.8V RWDM BTL Class-D power amplifier using an FGMOS comparator. 261-264
  
• Cheung Fai Lee, Philip K. T. Mok:
  On-chip current sensing technique for CMOS monolithic switch-mode power converters. 265-268
  
• Gerard Villar, Eduard Alarcón, Herminio Martínez, Domingo Biel, Eva Vidal, Alberto Poveda:
  Averaging circuit for switching power converter control: a CMOS current-mode integrated implementation. 269-272
  
• Stephen P. Carullo, Chika O. Nwankpa:
  Analysis of measurement delay errors in an Ethernet based communication infrastructure for power systems. 273-276
  
• Chris J. Dafis, Chika O. Nwankpa:
  A nonlinear observability formulation for power systems incorporating generator dynamics. 277-280
  
• Somchart Chokchaitam, Masahiro Iwahashi:
  Lossless/lossy coding gain to evaluate coding performance of the lossless/lossy wavelet. 281-284
  
• X. M. Xie, S. C. Chan, T. I. Yuk:
  On the theory and design of a class of perfect-reconstruction nonuniform cosine-modulated filter-banks. 285-288
  
• H. Johansson:
  Multirate approximately linear-phase IIR filter structures for arbitrary bandwidths. 289-292
  
• Behrouz Nowrouzian, Arthur T. G. Fuller, M. N. S. Swamy:
  An alternative approach to the design and synthesis of higher-order Bode-type variable-amplitude wave-digital equalizers. 293-296
  
• Shin'ichi Shiraishi, Miki Haseyama, Hideo Kitajima:
  A cost-effective and high-precision architecture for CORDIC-based adaptive lattice filters. 297-300
  
• Robert J. Butera, N. McSpadden, J. Mason:
  Theory and design of a bio-inspired multistable oscillator. 301-304
  
• Herbert H. C. Iu, C. K. Tse, V. Pjevalica, Y. M. Lai:
  Analysis of Hopf bifurcation in parallel-connected boost converters via averaged models. 305-308
  
• Y. Aruga, T. Endo, A. Hasegawa:
  Bifurcation of modes in three-coupled oscillators with the increase of nonlinearity. 309-312
  
• S. Moro, T. Matsumoto:
  Phase pattern switching in star-coupled Wien-bridge oscillators driven by pulse train. 313-316
  
• Masayuki Yamauchi, Yoshifumi Nishio, Akio Ushida:
  Analysis of phase-waves in coupled oscillators as a ladder. 317-320
  
• Bogdan J. Falkowski, Susanto Rahardja:
  Boolean verification with fastest LIA transforms. 321-324
  
• Jiann-Chyi Rau, Y. M. Chen, Shih-Chieh Chang:
  A don't-care based image circuit for function verification. 325-328
  
• Yutao Hu, Kartikeya Mayaram:
  An efficient algorithm for large-signal frequency-domain coupled device and circuit simulation [RF circuits]. 329-332
  
• A. Salem:
  Semi-formal verification of VHDL-AMS descriptions. 333-336
  
• Yi Feng, Eduard Cerny:
  Variable ordering on multiway decision graphs. 337-340
  
• Aloys Mvuma, Shotaro Nishimura, Takao Hinamoto:
  Adaptive optimization of notch bandwidth of an IIR filter used to suppress narrow-band interference. 341-344
  
• Mariane R. Petraglia, R. T. B. Vasconcellos:
  Steady-state analysis of a subband adaptive algorithm with critical sampling. 345-348
  
• Wei Xing Zheng:
  An alternative method for noisy autoregressive signal estimation. 349-352
  
• Yusuke Tsuda, Tetsuya Shimamura:
  An improved NLMS algorithm for channel equalization. 353-356
  
• Shu Hung Leung, Y. Xiong, J. F. Weng, C. F. So, W. H. Lau:
  Performance analysis of nonlinear RLS in mixture noise. 357-360
  
• J. M. Pierre Langlois, Dhamin Al-Khalili:
  Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity. 361-364
  
• Wang-Chi Cheng, Cheong-fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun:
  A 1.2 V 900 MHz CMOS mixer. 365-368
  
• Francisco Cardells-Tormo, A. Valls-Coquillat:
  Optimized FPGA-implementation of quadrature DDS. 369-372
  
• Byung-Do Yang, Lee-Sup Kim, Hyun-Kyu Yu:
  A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator. 373-376
  
• M. A. R. Eltokhy, Boon-Keat Tan, T. Matsuoka, K. Taniguchi:
  A 3.4-mW 128-MHz analog correlator for DS-CDMA wireless applications. 377-380
  
• K. Aoyama:
  A reconfigurable logic circuit based on threshold elements with a controlled floating gate. 381-384
  
• Yngvar Berg, Øivind Næss, Snorre Aunet, Renè Jensen, Mats Høvin:
  Novel floating-gate multiple-valued signal to binary signal converters for multiple-valued CMOS logic. 385-388
  
• Esther Rodríguez-Villegas, José M. Quintana, Maria J. Avedillo, Adoración Rueda:
  High-speed low-power logic gates using floating gates. 389-392
  
• Trond Ytterdal, Snorre Aunet:
  Compact low-voltage self-calibrating digital floating-gate CMOS logic circuits. 393-396
  
• Mats Høvin, Dag T. Wisland, Yngvar Berg, Tor Sverre Lande:
  A low-voltage sinc/sup 2/ decimator implemented by a new circuit technique using floating-gate MOS transistors. 397-400
  
• A. Costantini, P. A. Traverso, G. Vannini:
  Power amplifier ACPR simulation using standard harmonic balance tools. 401-404
  
• J. Shorb, David J. Allstot, R. Roze:
  Class AB-D-G line driver for central office asymmetric digital subscriber line systems. 405-408
  
• Mohammad B. Vahidfar, Armin Tajalli, Seyed Mojtaba Atarodi:
  A low-power subscriber line interface circuit in a high-voltage CMOS technology. 409-412
  
• T. Bourdi, A. Borjak, Izzet Kale:
  Agile multi-band delta-sigma frequency synthesizer architecture. 413-416
  
• M. Schobinger, S. R. Meier:
  A low-cost point-to-multi-point access system based on OFDM transmission. 417-420
  
• U. Singh, M. Green:
  Dynamics of high-frequency CMOS dividers. 421-424
  
• J. Van den Keybus, B. Bolsens, Johan Driesen, Ronnie Belmans:
  Power line communication front-ends based on ADSL technology. 425-428
  
• Esa Tiiliharju, Kari Halonen:
  A quadrature-modulator for 0.6-2.6 GHz with frequency doubler. 429-432
  
• Alyssa B. Apsel, Andreas G. Andreou, J. Liu:
  A 6 channel array of 5 milliwatt, 500 MHz optical receivers in .5 /spl mu/m SOS CMOS. 433-436
  
• Mostafa M. El Said, M. L. Elmasry:
  An improved ROM compression technique for direct digital frequency synthesizers. 437-440
  
• Patrick Mitran, Felix Beaudoin, Mourad N. El-Gamal:
  A 2.5 Gbit/s CMOS optical receiver frontend. 441-444
  
• Jongrit Lerdworatawee, Won Namgoong:
  MMSE matching for low noise amplifier. 445-448
  
• Aleksandar Tasic, Wouter A. Serdijn:
  Concept of spectrum-signal transformation. 449-452
  
• Cheng-Shing Wu, An-Yeu Wu:
  A novel cost-effective multi-path adaptive interpolated FIR (IFIR)-based echo canceller. 453-456
  
• S. Soliman, F. Yuan, Kaamran Raahemifar:
  An overview of design techniques for CMOS phase detectors. 457-460
  
• V. Balan, T. Pan:
  A crystal oscillator with automatic amplitude control and digitally controlled pulling range of +-100 ppm. 461-464
  
• M. Kaneko, J. Yokoyama, S. Tayu:
  3D scheduling based on code space exploration for dynamically reconfigurable systems. 465-468
  
• Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha:
  Performance optimization of multiple memory architectures for DSP. 469-472
  
• Cesare Alippi, Andrea Galbusera, Marco Stellini:
  An application level synthesis methodology for embedded systems. 473-476
  
• Jochen Mades, D. E. Schwarz, Manfred Glesner:
  A discrete algorithm for the regularization of hierarchical VHDL-AMS models. 477-480
  
• Yoonseo Choi, Taewhan Kim:
  Address code optimization using code scheduling for digital signal processors. 481-484
  
• D. W. Graham, P. Hasler:
  Capacitively-coupled current conveyer second-order section for continuous-time bandpass filtering and cochlea modeling. 485-488
  
• Paul D. Smith, Matt Kucic, Paul E. Hasler:
  Accurate programming of analog floating-gate arrays. 489-492
  
• C. Duffy, Ethan Farquhar, Paul E. Hasler:
  Practical issues using e-pot circuits. 493-496
  
• Hiroki Sato, Akira Hyogo, Keitaro Sekine:
  A V/sub t/-zero equivalent MOSFET and its applications. 497-500
  
• Johannes Goplen Lomsdalen, Yngvar Berg, Renè Jensen:
  A low-voltage floating-gate CMOS transconductance amplifier, and a spin-off quasi frequency tripler. 501-504
  
• Tadashi Suetsugu, Marian K. Kazimierczuk:
  Voltage-clamped class E amplifier with a Zener diode across the choke coil. 505-508
  
• D. V. Chernov, Marian K. Kazimierczuk, V. G. Krizhanovski:
  Class-E MOSFET low-voltage power oscillator. 509-512
  
• Alberto Reatti, L. Pellegrini, Marian K. Kazimierczuk:
  Impact of boost converter parameters on open-loop dynamic performance for DCM. 513-516
  
• A. N. Rudiakova, Marian K. Kazimierczuk, J. V. Rassokhin, V. G. Krizhanovski:
  Class-N high-frequency power amplifier. 517-520
  
• A. Alsharqawi, Issa Batarseh:
  Generalized state-plane analysis of soft-switching DC-DC converters. 521-524
  
• K. Rustom, Wenkai Wu, Weihong Qiu, Issa Batarseh:
  Asymmetry half bridge soft-switching PFC converter with direct energy transfer. 525-528
  
• Ming-Dou Ker, Kuo-Chun Hsu:
  On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process. 529-532
  
• Ming-Dou Ker, Che-Hao Chuang:
  ESD protection circuits with novel MOS-bounded diode structures. 533-536
  
• Jeng-Jie Peng, Ming-Dou Ker, Hsin-Chin Jiang:
  Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits. 537-540
  
• Li Ding, Pinaki Mazumder:
  Modified long channel model for analytical study of DSM circuits. 541-544
  
• Kyeong-Sik Min, Young-Hee Kim, Jin-Hong Ahn, Jin-Yong Chung, Takayasu Sakurai:
  CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits. 545-548
  
• Jiun-In Guo, Chien-Chang Lin:
  A new hardware efficient design for the one dimensional discrete Fourier transform. 549-552
  
• E. Marconetti, R. Guenard, D. Savage, P. Crowe, I. Epelde, L. Bradley, Fabrizio Calì:
  A fully programmable Reed Solomon 8-bit codec based on a re-shaped Berlekamp Massey algorithm. 553-556
  
• Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu:
  Memory arrangements in turbo decoders using sliding-window BCJR algorithm. 557-560
  
• Jung Hoo Lee, Jae Sung Lee, Myung Hoon Sunwoo, Kyung Ho Kim:
  Design of new DSP instructions and their hardware architecture for the Viterbi decoding algorithm. 561-564
  
• Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen:
  Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method. 565-568
  
• Devrim Yilmaz Aksin, Franco Maloberti:
  Very high-speed BJT buffer for track-and-hold amplifiers with enhanced linearity. 569-572
  
• F. Vessal, C. Andre T. Salama:
  A bipolar 2-GSample/s track-and-hold amplifier (THA) in 0.35 /spl mu/m SiGe technology. 573-576
  
• Darius Jakonis, Christer Svensson:
  A 1 GHz linearized CMOS track-and-hold circuit. 577-580
  
• Preetam Tadeparthy, M. Das:
  Techniques to improve linearity of CMOS sample-and-hold circuits for achieving 100 dB performance at 80 MSps. 581-584
  
• Sameer R. Sonkusale, Jan Van der Spiegel:
  A low distortion MOS sampling circuit. 585-588
  
• Huanzhang Huang, E. K. Lee:
  Frequency and Q tuning techniques for continuous-time bandpass sigma-delta modulator. 589-592
  
• Bo Xia, Shouli Yan, Edgar Sánchez-Sinencio:
  An auto-tuning structure for continuous time sigma-delta AD converter and high precision filters. 593-596
  
• A. D. Fifield, D. K. Allee:
  Dynamic tuning of the noise transfer function of high order delta-sigma analog to digital converters. 597-600
  
• Aydin I. Karsilayan, Taner Sumesaglam:
  Digital tuning of continuous-time high-Q filters. 601-604
  
• J. R. Moritz, Y. Sun:
  Automatic tuning of high frequency, high Q, multiple loop feedback bandpass filters. 605-608
  
• Christal Gordon, Paul E. Hasler:
  Biological learning modeled in an adaptive floating-gate system. 609-612
  
• Ricardo Carmona, Francisco Jiménez-Garrido, Rafael Domínguez-Castro, Servando Espejo-Meana, Ángel Rodríguez-Vázquez:
  Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics. 613-616
  
• Mats Høvin, Dag T. Wisland, Yngvar Berg, J. T. Marienborg, Tor Sverre Lande:
  Delta-sigma modulation in single neurons. 617-620
  
• Sandro A. P. Haddad, Wouter A. Serdijn:
  Mapping the wavelet transform onto silicon: the dynamic translinear approach. 621-624
  
• Toshihiko Yamasaki, T. Taguchi, Tadashi Shibata:
  Low-power CDMA analog matched filters based on floating-gate technology. 625-628
  
• Lei Gao, Lina J. Karam, Martin Reisslein, Glen P. Abousleman:
  Error-resilient image coding and transmission over wireless channels. 629-632
  
• M. Mowafi, Nan Jiang, Thomas P. Caudell, Wei Shu, Min-You Wu:
  Real-time transmission of stereo images over the access grid. 633-636
  
• Ch. V. Verikoukis:
  An adaptive control of the request access bandwidth of the DQRUMA for providing the QoS in an OFDM-based W-ATM system. 637-640
  
• Hua Cai, Guobin Shen, Zixiang Xiong, Shipeng Li, Bing Zeng:
  An optimal packetization scheme for fine granularity scalable bitstream. 641-644
  
• Li Ding, Pinaki Mazumder, David Blaauw:
  Crosstalk noise estimation using effective coupling capacitance. 645-648
  
• H. Kubota, A. Kamo, T. Watanabe, H. Asai:
  Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique. 649-552
  
• Yehea I. Ismail:
  Evaluating noise pulses in RC networks due to capacitive coupling. 653-656
  
• Chao Xu, F. Barber, K. R. Laker, Jan Van der Spiegel:
  Analysis of clock buffer phase noise. 657-660
  
• Paolo Gastaldo, Rodolfo Zunino:
  Hausdorff distance for target detection. 661-664
  
• Ibrahim Cem Baykal, Roberto Muscedere, Graham A. Jullien:
  On the use of hash functions for defect detection in textures for in-camera web inspection systems. 665-668
  
• Liang Tao, H. K. Kwan:
  Automatic localization of human eyes in complex background. 669-672
  
• Madhusudhana Gargesha, Sethuraman Panchanathan:
  Face detection from color images by iterative thresholding on skin probability maps. 673-676
  
• Yih-Haw Jan, David W. Lin:
  Extraction of video objects by combined motion and edge analysis. 677-680
  
• Johan Driesen, Ronnie Belmans:
  Time-frequency analysis in power measurement using complex wavelets. 681-684
  
• Lisandro Lovisolo, Eduardo A. B. da Silva, Marco A. M. Rodrigues, Paulo S. R. Diniz:
  Coherent decompositions of power systems signals using damped sinusoids with applications to denoising. 685-688
  
• Hanoch Lev-Ari, Alex M. Stankovic:
  Defining reactive power in circuit transients via local Fourier coefficients. 689-692
  
• Vaibhav Donde, Ian A. Hiskens:
  Analysis of limit cycle stability in a tap-changing transformer. 693-696
  
• Jie Wan, Karen Nan Miu:
  Zonal load estimation studies in radial power distribution networks. 697-700
  
• Soo-Chang Pei, Peng-Hua Wang:
  Maximally flat allpass fractional Hilbert transformers. 701-704
  
• Hiroshi Hasegawa, M. Nakagawa, Isao Yamada, Kohichi Sakaniwa:
  A truncated polynomial interpolation theorem and its application to the WLS design of IIR filters. 705-708
  
• Takao Hinamoto, Hiroaki Ohnishi:
  Minimization of roundoff noise in state-space digital filters using error feedback and coordinate transformation. 709-712
  
• Chien-Cheng Tseng:
  Design of variable fractional delay allpass filter using weighted least squares method. 713-716
  
• Andrzej Tarczynski:
  Problem dimensionality reduction in design of optimal IIR filters. 717-720
  
• L. Schwoerer:
  VLSI suitable synchronization algorithms and architecture for IEEE 802.11a Physical Layer. 721-724
  
• A. Kansal, Uday B. Desai:
  Mobility support for Bluetooth public access. 725-728
  
• Myoung-Cheol Shin, Seong-Il Park, Sung-Won Lee, Se-Hyeon Kang, In-Cheol Park:
  Area-efficient digital baseband module for Bluetooth wireless communications. 729-732
  
• Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang:
  An area-efficient systolic division circuit over GF(2/sup m/) for secure communication. 733-736
  
• D. A. F. Ei-Dib, Mohamed I. Elmasry:
  Low-power register-exchange Viterbi decoder for high-speed wireless communications. 737-740
  
• Shuqing Zhao, Daniel Gajski:
  Modeling a new RTL semantics in C++. 741-744
  
• Sudha Kannurao, Bogdan J. Falkowski:
  Identification of complement single variable symmetry in Boolean functions through Walsh transform. 745-748
  
• T. Ozawa:
  Efficient algorithms for planar embedding of graphs with constraints in placing specified vertices on face boundaries. 749-752
  
• Bogdan J. Falkowski:
  Algorithms for fast arithmetic transform. 753-756
  
• Bogdan J. Falkowski:
  Generalized multi-polarity Haar transform. 757-760
  
• K. S. Yeung, S. C. Chan:
  Design and implementation of multiplier-less tunable 2-D FIR filters using McClellan transformation. 761-764
  
• Abdellah Kacha, Khier Benmahammed:
  Tracking instantaneous frequency using two-sided linear prediction. 765-768
  
• A. Yonemoto, Takashi Hisakado, Kohshi Okumura:
  An improvement of convergence of FFT-based numerical inversion of Laplace transforms. 769-772
  
• Andrew G. Dempster, Süleyman Sirri Demirsoy, Izzet Kale:
  Designing multiplier blocks with low logic depth. 773-776
  
• Masayuki Kawamata, Shunsuke Koshita:
  On the invariance of second-order modes under frequency transformation in 2-D separable denominator digital filters. 777-780
  
• Arash Reyhani-Masoleh, M. Anwar Hasan:
  Efficient digit-serial normal basis multipliers over GF(2/sup m/). 781-784
  
• Zhan Yu:
  Low power finite field multiplication and division in re-configurable Reed-Solomon codec. 785-788
  
• Zhiyuan Yan, Dilip V. Sarwate:
  Systolic architectures for finite field inversion and division. 789-792
  
• Jae Hyun Baek, J. Y. Kang, Myung Hoon Sunwoo:
  Design of a high-speed Reed-Solomon decoder. 793-796
  
• Marcus Bednara, M. Daldrup, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi:
  Tradeoff analysis of FPGA based elliptic curve cryptography. 797-800
  
• Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re:
  Power characterization of digital filters implemented on FPGA. 801-804
  
• Júlio C. B. de Mattos, Luigi Carro:
  Efficient architecture for FPGA-based microcontrollers. 805-808
  
• Chuanjun Zhang, Frank Vahid:
  A power-configurable bus for embedded systems. 809-812
  
• Wei Wang, M. N. S. Swamy, M. Omair Ahmad:
  A new architecture of RRNS error-correcting QC encoder/decoder and its FPGA implementation. 813-816
  
• Kahou Wong:
  Stability study of a voltage-mode buck regulator using system poles approach. 817-820
  
• Edith Kussener, Hervé Barthélemy, A. Malherbe, A. Kaiser:
  Versatile macromodel for the power supply of submicronic CMOS microprocessors based on voltage down DC-DC converter. 821-824
  
• C. K. Chava, J. Silva-Martinez:
  A robust frequency compensation scheme for LDO regulators. 825-828
  
• Itsda Boonyaroonate, S. Mori:
  A compact DC/AC inverter for automotive application. 829-832
  
• Siew Kuok Hoon, Jun Chen, Franco Maloberti:
  An improved bandgap reference with high power supply rejection. 833-836
  
• R. Echavarría, V. Sanchez, Mario Ponce, M. Cotorogea, A. Claudio:
  Analysis of a power topology for a quasi-resonant fast on-load tap changing regulator. 837-840
  
• Brad Bryant, Marian K. Kazimierczuk:
  Derivation of the buck-boost PWM DC-DC converter circuit topology. 841-844
  
• R. Razali, V. Subbiah, M. A. Choudhury, R. Yusof:
  Performance analysis of online dual slope delta modulated PWM inverter. 845-848
  
• Alberto Reatti, L. Pellegrini, Marian K. Kazimierczuk:
  Measurement of open-loop small-signal control-to-output transfer function of a PWM boost converter operated in DCM. 849-851
  
• J. Morud:
  A 1 MHz voltage multiplier design. 856-859
  
• Santanu Mahapatra, Adrian M. Ionescu, Kaustav Banerjee, Michel J. Declercq:
  A SET quantizer circuit aiming at digital communication system. 860-863
  
• Tetsuya Uemura, Pinaki Mazumder:
  Rise time analysis of MOBILE circuit. 864-867
  
• R. van de Haar, J. Hoekstra, R. H. Klunder:
  A SPICE model for single electronics. 868-871