ISCAS 1995:
Seattle,
WA,
USA - Volume 3
1995 IEEE International Symposium on Circuits and Systems,
ISCAS 1995,
Seattle,
Washington,
USA,
April 30 - May 3,
1995. IEEE,
1995,
ISBN 0-7803-2570-2,
Volume 3
7A:
Operational Amplifiers 1
7B:
Low-Power Circuits
7C:
Analog Device and Behavioral Modeling
7D:
Adaptive Filters 2
7E:
Vector Quantization for Video Coding
7F:
Aspects of Linear Circuits and Systems
7G:
Analog VLSI Neural Networks
- Paul E. Hasler, Chris Diorio, Bradley A. Minch, Carver Mead:
Single Transistor Learning Synapse with Long Term Storage.
1660-1663
- Bing J. Sheu, Theodore W. Berger, Tony H. Wu, Richard H. Tsai:
VLSI Neural Network Implementation of a Hippocampal Model.
1664-1667
- Yngvar Berg, Jon-Erik Ruth, Tor Sverre Lande:
Scalable Mean Rate Signal Encoding Analog Neural Network.
1668-1671
- Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
Experimental Results of an Analog Current-Mode ART1 Chip.
1672-1675
- Jeng-Feng Lan, Chung-Yu Wu:
CMOS Current-Mode Outstar Neural Networks with Long-Period Analog Ratio Memory.
1676-1679
7H:
VLSI Routing and Extraction
7S:
Radial Basis Function Neural Networks 1
8A:
Operational Amplifiers 2
8B:
VLSI Timing
8C:
Analog Simulation
8D:
Adaptive Filters 4
8E:
Subband Transforms for Video Coding
8F:
General Distributed/Power Systems
8G:
Neural Network Classifiers
8H:
Interconnect Simulation
- Jun-Fa Mao, Omar Wing, Fung-Yuel Chang:
Time-Domain Model of Transmission Lines with Arbitrary Initial Potential and Current Distributions for Transient Analysis.
1832-1835
- Nishath K. Verghese, David J. Allstot:
A Macromodel Compaction Scheme for the Fast Stimulation of Large Linear Mesh Circuits.
1836-1839
- S. Cyrusian:
Time Domain Based Modeling of Lossy Coupled Transmission Lines by Approximation of Transfer Functions.
1840-1843
- Scott D. Huss:
A Mathematical and Lumped-Element Model for Multiple Cascaded Lossy Transmission Lines with Arbitrary Impedances and Discontinuities.
1844-1847
8P.1:
Analog Circuits and Signal Processing
- Yuming Cao, Gabor C. Temes:
CMOS Circuits for On-Chip Capacitance Ratio Testing or Sensor Readout.
1848-1851
- Edmund Pierzchala, Rolf Schaumann, Paul Van Halen, Stanislaw Szczepanski, Marek A. Perkowski:
Highly Linear VHF Current-Mode Miller Integrator with 900 dB DC Gain.
1852-1855
- G. H. M. Joordens, Johannes A. Hegt, Domine Leenaerts:
A High Performance Low Voltage Switched-Current Multiplier.
1856-1859
- T. Maurel, R. Bouchakour, Christophe Lallement:
One-Dimensional Model of the Power Bipolar Transistor with Thermoelectrical Interactions for Circuit Applications.
1860-1863
- Jay L. Brown:
High Sensitivity Magnetic Field Sensor Using GMR Materials with Integrated Electronics.
1864-1867
- José Silva-Martínez, Jorge Salcedo-Suñer:
A CMOS Preamplifier for Electret Microphones.
1868-1871
- T. L. Lim, David G. Haigh, D. R. Webster:
On the Design of Active GaAs Multipliers.
1872-1875
8P.2:
Digital Signal Processing
- Soo-Chang Pei, Min-Hung Yeh:
Time Frequency Split Zak Transform for Finite Gabor Expansion.
1876-1879
- J. A. Draidi, L. M. Khadra, M. A. Khasawneh:
Generalized Cone-Shaped Kernels for Time-Frequency Distributions.
1880-1883
- Wai-Hung Leung, Fung-Yuel Chang:
Transient Analysis Via Fast Wavelet-Based Convolution.
1884-1887
- X. Q. Gao, H. Zhang, Z. Y. He:
Subband Model and Implementation of 0-QAM System.
1888-1891
- Daniel Pak-Kong Lun, Tai-Chiu Hsung, Wan-Chi Siu:
On the Convolution Property of a New Discrete Radon Transform and its Efficient Inversion Algorithm.
1892-1895
- Dinu Coltuc, Ioannis Pitas:
Jordan Decomposition Filters.
1896-1899
- Jaakko Astola, Pauli Kuosmanen, David Akopian, David Z. Gevorkian:
Fibonacci P-Code Method for Generalized Stack Filtering.
1900-1903
- Ram G. Shenoy:
Model-Matching Design of Sample-Rate Changers: Asymptotic Analysis.
1904-1907
- Eduard Krajnik:
On Time-Domain Deconvolution and the Computation of the Cepstrum.
1908-1911
8P.4:
VLSI Self-Test
8P.5:
Digital Communication and Coding
8S:
Radial Basis Function Neural Networks 2
9A:
Analog Techniques 1
- Chung-Yu Wu, Shuo-Yuan Hsiao, Ron-Yi Liu:
A 3-V 1-GHz Low-Noise Bandpass Amplifier.
1964-1967
- M. Jamal Deen, Duljit S. Malhi, Zhixin Yan, Robert A. Hadaway:
A New Mixer Circuit Using a Gate-Controlled LPNP BJT.
1968-1971
- Benjamin J. Blalock, Phillip E. Allen:
A Low-Voltage, Bulk-Driven MOSFET Current Mirror for CMOS Technology.
1972-1975
- Fan You, Sherif H. K. Embabi, Edgar Sánchez-Sinencio, A. Ganesan:
A Design Scheme to Stabilize the Active Gain Enhancement Amplifier.
1976-1979
- Giuseppe Caiulo, Piero Malcovati, C. Bona, Franco Maloberti:
Novel Circuit Solutions for Rail-to-Rail CMOS Buffer.
1980-1983
9B:
VLSI Arithmetics
9C:
Testing and Fault Simulation
9D:
Finite Word Effects in Digital Filters
9F:
Circuit Theory Aspects in Power Electronics 1
- Antonio Luchetta, Stefano Manetti, Maria Cristina Piccirilli, Alberto Reatti:
Frequency-Domain Analysis of DC/DC Converters Using a Symbolic Approach.
2043-2046
- Marian K. Kazimierczuk, Robert Cravens II:
Input Impedance of Closed-Loop PWM Buck-Boost DC-DC Coinverter for CCM.
2047-2050
- Y. S. Lee, K. W. Siu, Xuan-Zhong Liu:
Optimizing the Design of Switch-Mode Power Supplies with Battery Back-Up and Power Factor Correction.
2051-2054
- Roberto Giral, Luis Martínez, Javier Hernanz, Javier Calvente, Francesc Guinjoan, Alberto Poveda, R. Leyva:
Compensating Networks for Sliding-Mode Control.
2055-2058
9G:
Recent Advances in the SI Techniques
9H:
Symbolic Analysis Methods for Large Analog Integrated Circuits 1
- Marian Pierzchala, Benedykt Rodanski:
Obtaining Symbolic Network Functions of Large Circuits - An Algebraic Approach.
2075-2078
- Erich Wehrhahn:
Symbolic Analysis of Large Linear Circuits with the Bilinear-Splitting Transformation.
2079-2082
- Jer-Jaw Hsu, Carl Sechen:
Accurate Extraction of Simplified Symbolic Pole/Zero Expressions for Large Analog IC's.
2083-2087
- Qicheng Yu, Carl Sechen:
Efficient Approximation of Symbolic Network Function Using Matroid Intersection Algorithms.
2088-2091
9S:
Spatio-Temporal and Neuro-Fuzzy CMOS Chips:
Design and Implementation 1
10A:
Analog Techniques 2
10B:
VLSI Self-Test
10C:
Analog Synthesis and Test
10D:
Transforms and Logic Functions
10F:
Circuit Theory Aspects in Power Electronics 2
10G:
Neural Architectures and Implementations
- Emil M. Petriu, Kenzo Watanabe, Tet H. Yeap, Satomi Ogawa:
Neural Network Architecture Using Random-Pulse Data Processing.
2185-2188
- Mario Costa, Davide Palmisano, Eros Pasero:
NESP: An Analog Neural Signal Processor.
2189-2192
- Daniel Mange, Serge Durand, Eduardo Sanchez, André Stauffer, Gianluca Tempesti, Pierre Marchal, Christian Piguet:
A New Paradigm for Developing Digital Systems Based on a Multi-Cellular Organization.
2193-2196
- Cesare Alippi, Raffaele Petracca, Vincenzo Piuri:
Off-Line Performance Maximisation in Feed-Forward Neural Networks by Applying Virtual Neurons and Covariance Transformations.
2197-2200
- Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.:
Fault-Tolerant Neural Architectures: The Use of Rotated Operands.
2201-2204
10H:
Symbolic Analysis Methods for Large Analog Integrated Circuits 2
- Georges G. E. Gielen, Geert Debyser, Piet Wambacq, Koen Swings, Willy M. C. Sansen:
Use of Symbolic Analysis in Analog Circuit Synthesis.
2205-2208
- A. Liberatore, Antonio Luchetta, Stefano Manetti, Maria Cristina Piccirilli:
A New Symbolic Program of Package for the Interactive Design of Analog Circuits.
2209-2212
- M. Helena Fino, José E. da Franca, Adolfo Steiger-Garção:
Automatic Symbolic Characterization of SC Multirate Circuits with Finite Grain Operational Amplifiers.
2213-2216
- A. Konczykowska, Wlodzimierz M. Zuberek:
Function Evaluation in Symbolic Analysis.
2217-2220
- M. A. Styblinski, Ming Qu:
Comparison of Symbolic Approximation and Macromodelling Techniques for Statistical Design of Analog Integrated Circuits.
2221-2224
10P.1:
Analog Circuits and Signal Processing
- Erik J. Hogenbirk, Huibert-Jan Verhoeven, Johan H. Huijsing:
An Integrated Smart Sensor for Flow and Temperature with I2C Bus Interface: FTS2.
2225-2228
- Ahmad Baghai Dowlatabadi, J. Alvin Connelly:
A New Offset Cancellation Technique for CMOS Differential Amplifiers.
2229-2232
- Chris Diorio, Sunit Mahajan, Paul E. Hasler, Bradley A. Minch, Carver Mead:
A High-Resolution Non-Volatile Analog Memory Cell.
2233-2236
- Manuel Delgado-Restituto, Rafael López de Ahumada, Ángel Rodríguez-Vázquez:
Secure Communication Through Switched-Current Chaotic Circuits.
2237-2240
- A. Häberli, Piero Malcovati, D. Jäggi, Henry Baltes, Franco Maloberti:
High Dynamic Range Interface System for a Micromachined Integrated AC-Power Sensor.
2241-2244
- J. Francisco Duque-Carrillo, Guido Torelli, R. Pérez-Aloe, J. M. Valverde, Franco Maloberti:
A Class of Fully-Differential Basic Building Blocks Based on Unity-Gain Differnence Feedback.
2245-2248
- Bradley A. Minch, Chris Diorio, Paul E. Hasler, Carver Mead:
A vMOS Soft-Maximum Current Mirror.
2249-2252
- Lu Yue, John I. Sewell:
A Systematic Approach for Ladder Based Switched-Current Filter Design.
2253-2256
- Lu Yue, John I. Sewell:
Multirate SC and SI Filter System Design by XFILT.
2257-2260
10P.2:
Digital Signal Processing
- W. K. Lai, P. C. Ching:
Blind Estimation Using Higher-Order Cumulants.
2261-2264
- Karen Egiazarian, Jaakko Astola, Sos S. Agaian:
Spectral Approach to Logical Distribution-Free Classification Problem.
2265-2268
- Ying-Chang Liang, Yan-Da Li, Xian-Da Zhang:
EAMUSE: An Extended Algorithm for Multiple Sources Extraction.
2269-2272
- Petar M. Djuric:
A Bayesian Model Order Determination Rule for Harmonic Signals.
2273-2276
- Rajeev Agarwal, Eugene I. Plotkin, M. N. S. Swamy:
Statistically Optimal Null Filters for Processing Short Record Length Signals.
2277-2280
- Takayuki Nakachi, Nozomu Hamada, Katsumi Yamashita:
The AR Modeling of Two-Dimensional Fields by Extended Lattice Filter.
2281-2284
- Stefan Oberle, August Kaelin:
Recognition of Acoustical Alarm Signals for the Profoundly Deaf Using Hidden Markov Models.
2285-2288
- Hsiang-Tsun Li, Petar M. Djuric:
A Novel Approach to Detection of Closely Spaced Sinisoids.
2289-2292
- F. L. Hui, Wing Hong Lau, Shu Hung Leung, Andrew Luk:
Sequential Detection Using a New Recursive-Averaging Cumulant Estimation Method.
2293-2296
10P.4:
VLSI Architectures and Systems
- Akihisa Yamada, Satoru Nakamura, Nagisa Ishiura, Isao Shirakawa, Takashi Kambe:
Optimal Scheduling for Conditional Recource Sharing.
2297-2300
- Kevin J. Nowka, Michael J. Flynn:
System Design Using Wave-Pipelining: A CMOS VLSI Vector Unit.
2301-2304
- Michael B. Kleiner, Stefan A. Kühn, Werner Weber:
Performance Improvement of the Memory Hierarchy of RISC Systems by Applications of 3-D Technology.
2305-2308
- De-Sheng Chen, Majid Sarrafzadeh, Gary K. H. Yeap:
State Encoding of Finite State Machines for Low Power Design.
2309-2312
- Shousheng He, Mats Torkelson:
A Pipelined Bit-Serial Complex Multiplier Using Distributed Arithmetic.
2313-2316
10S:
Spatio-Temporal and Neuro-Fuzzy CMOS Chips:
Design and Implementation 2
- G. Moon, Mona E. Zaghloul, R. W. Newcomb, J. S. Yoo:
Pulse Duty Cycle Neural Processing Element Applied to Autotracking Model.
2317-2320
- S. Ahmadi, Louiza Sellami, R. W. Newcomb:
A CMOS PWL Fuzzy Membership Function.
2321-2324
- Ángel Rodríguez-Vázquez, Fernando Vidal-Verdú:
Learning in Neuro/Fuzzy Analog Chips.
2325-2328
- Fathi M. A. Salam, Gamze Erten:
An Adaptive Neuro/Fuzzy CMOS Chip.
2329
- Swapan Saha, V. Vittal, W. Kliemann, A. A. Fouad:
Local Approximation of Stability Boundary of a Power System Using the Real Normal Form of Vector Fields.
2330-2333
- Henry Chung, Adrian Ioinovici:
Design Constraint on Feedback Gain Vector of Switching Regulators for Local Stability.
2334-2337
- Faouzi Kossentini, Mark J. T. Smith, Allen Scales:
High Order Entropy-Constrained Residual VQ for Lossless Compression of Images.
2338-2341
Copyright © Mon Nov 2 20:52:27 2009
by Michael Ley (ley@uni-trier.de)
