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ISCAS 1995: Seattle, WA, USA - Volume 3

1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995. IEEE, 1995, ISBN 0-7803-2570-2, Volume 3

7A: Operational Amplifiers 1

7B: Low-Power Circuits

7C: Analog Device and Behavioral Modeling

7D: Adaptive Filters 2

7E: Vector Quantization for Video Coding

7F: Aspects of Linear Circuits and Systems

7G: Analog VLSI Neural Networks

7H: VLSI Routing and Extraction

7S: Radial Basis Function Neural Networks 1

8A: Operational Amplifiers 2

8B: VLSI Timing

8C: Analog Simulation

8D: Adaptive Filters 4

8E: Subband Transforms for Video Coding

8F: General Distributed/Power Systems

8G: Neural Network Classifiers

8H: Interconnect Simulation

8P.1: Analog Circuits and Signal Processing

8P.2: Digital Signal Processing

8P.4: VLSI Self-Test

8P.5: Digital Communication and Coding

8S: Radial Basis Function Neural Networks 2

9A: Analog Techniques 1

9B: VLSI Arithmetics

9C: Testing and Fault Simulation

9D: Finite Word Effects in Digital Filters

9F: Circuit Theory Aspects in Power Electronics 1

9G: Recent Advances in the SI Techniques

9H: Symbolic Analysis Methods for Large Analog Integrated Circuits 1

9S: Spatio-Temporal and Neuro-Fuzzy CMOS Chips: Design and Implementation 1

10A: Analog Techniques 2

10B: VLSI Self-Test

10C: Analog Synthesis and Test

10D: Transforms and Logic Functions

10F: Circuit Theory Aspects in Power Electronics 2

10G: Neural Architectures and Implementations

10H: Symbolic Analysis Methods for Large Analog Integrated Circuits 2

10P.1: Analog Circuits and Signal Processing

10P.2: Digital Signal Processing

10P.4: VLSI Architectures and Systems

10S: Spatio-Temporal and Neuro-Fuzzy CMOS Chips: Design and Implementation 2

Copyright © Mon Nov 2 20:52:27 2009 by Michael Ley (ley@uni-trier.de)