ISCAS 1995:
Seattle,
WA,
USA - Volume 1
1995 IEEE International Symposium on Circuits and Systems,
ISCAS 1995,
Seattle,
Washington,
USA,
April 30 - May 3,
1995. IEEE,
1995,
ISBN 0-7803-2570-2,
Volume 1
Delta-Sigma Techniques I
VLSI Circuits I
- Anura P. Jayasumana, Yashwant K. Malaiya, Sankaran M. Menon:
A Novel High-Speed BiCMOS Domino Logic Family.
21-24
- Chung-Yu Wu, Jr-Houng Lu, Kuo-Hsing Cheng:
A New CMOS Current-Sensing Complementary Pass-Transistor Logic (CSCPTL) for High-Speed Low-Voltage Applications.
25-28
- J. A. Hidalgo-López, J. C. Tejero, J. Fernández, A. Gago:
New Types of Digital Comparators.
29-32
- R. X. Gu, Mohamed I. Elmasry:
Power Dissipation in Deep Submicron CMOS Digital Circuits.
33-36
- Stefan A. Kühn, Michael B. Kleiner, Roland Thewes, Werner Weber:
Vertical Signal Transmission in Three-Dimensional Integrated Circuits by Capacitive Coupling.
37-40
Floorplanning and Module Generation
Novel IIR and FIR Implementations I
Wideband Communication
- XuDuan Lin, KyungHi Chang, Jaeseok Kim:
Optimal PN Sequences Design for Quasi-Synchronous CDMA Communication Systems.
81-84
- C. A. Carty, M. M. Jamali, A. G. Eldin, Subhash C. Kwatra, R. E. Jones:
A High Speed 800 Channel Digital Interpolator Network.
85-88
- S. Subramanian, Dale J. Shpak, Andreas Antoniou:
Performance of a Quasi-Newton Adaptive Filtering Algorithm for a CDMA Indoor Wireless System.
89-92
- Nabil Abd Rabou, Hiroaki Ikeda, Hirofumi Yoshida:
Wideband Optical Fiber Signal Transmission System of 300MHz Bandwidth Using LED.
93-96
- Norman M. Filiol, Calvin Plett, Tom A. D. Riley, Miles A. Copeland:
Bit-Error Rate Measurements for A High Frequency Interpolated Frequency-Hopping Spread-Spectrum System.
97-100
Existence,
Uniqueness and Stability of DC Operating Points
- Arturo Sarmiento-Reyes:
A Novel Method to Predict Both, the Upper Bound on the Number and the Stability of DC Operating Points of Transistor Circuits.
101-104
- Michael M. Green:
A Method for Identifying Combinations of Transistors that can be Replaced with a Single Transistor when Applying the Nielsen-Willson Theorem.
105-108
- Robert M. Fox:
Design-Oriented Analysis of CD Operating-Point Instability.
109-112
- S. W. Ng, Y. S. Lee, C. K. Tse, S. C. Wong:
Stability of a Circuit with Parasitic Capacitances.
113-116
- Michael M. Green, Robert C. Melville:
Sufficient Conditions for Finding Multiple Operating Points for CD Circuits Using Continuation Methods.
117-120
Learning in Neural Networks
Global Bifurcations and Complex Nonlinear Phenomena in the Power System I
Combinatronics in Advanced CAS I
Delta-Sigma Techniques II
VLSI Clocking Circuits
Performance-Driven Routing
Novel IIR and FIR Implementations II
Image Processing and Compression
Aspects of Chaos
Implementation of Neural and Fuzzy Circuits
Global Bifurcations and Voltage Stability Phenomena in Electric Power Systems I
Analog Circuits and Signal Processing
- Chung-Yu Wu, Heng-Shou Hsu:
The Design of New Low-Voltage CMOS VHF Continuous-Time Lowpass Biquaud Filters.
295-298
- R. F. Wolffenbuttel, G. de Graaf, E. Engen:
Bipolar Circuits for Readout of an Integrated Silicon Color Sensor.
299-302
- Erik Bruun:
Bandwidth Limitations in Current Mode and Volage Mode Integrated Feedback Amplifiers.
303-306
- C. S. Choy, C. F. Chan, M. H. Ku:
A Feedback Control Circuit Design Technique to Suppress Power Noise in High Speed Output Driver.
307-310
- D. Perry, Gordon W. Roberts:
Log-Domain Filters Based on LC Ladder Synthesis.
311-314
- Giuseppe Di Cataldo, Giovanni Palmisano, Gaetano Palumbo:
A CMOS CCII+.
315-318
- Feng Wang, Ramesh Harjani:
Dynamic Amplifiers: Settling, Slewing and Power Issues.
319-322
- Peter Shah, Chris Toumazou:
A New BiCMOS Technique for Very Fast Discrete-Time Signal Processing.
323-326
Digital Signal Processing
- Roberto Manduchi:
2-D IFIR Structures Using Generalized Factorable Filters.
327-330
- Pavel Zahradnik, Rolf Unbehauen:
Frequency Shift of Two-Dimensional Real Coefficient Zero Phase Fir Digital Filters.
331-334
- Srikanth Pokala, Arnab K. Shaw:
Optimal Spatial-Domain Design Analogues in Optimal System Identification.
335-338
- H. Safiri, Majid Ahmadi, V. Ramachandran:
Design of 2-Dimensional Digital Filters Using 2-D All-Pass Building Blocks.
340-343
- Rajamohana Hegde, B. A. Shenoi:
Design of 2-D IIR Filters Using a New Digital Spectral Transformation.
344-347
- Takao Hinamoto, Shuji Karino, Naoki Kuroda:
Error Spectrum Shaping in 2-D Digital Filters.
348-351
- Haiyun Luo, Songwu Lu, Andreas Antoniou:
New Algorithm for Structurally Balanced Model Reduction of 2-D Discrete Systems.
352-355
- Haiyun Luo, Songwu Lu, Andreas Antoniou:
A Weighted Balanced Realization of 2-D Discrete Systems.
357-360
- Vesa Välimäki:
A New Filter Implementation Strategy for Lagrange Interpolation.
361-364
- Miki Haseyama, Tohru Hirohku, Hideo Kitajima:
A Realization Method of an ARMAX Lattice Filter.
365-368
VLSI CAD
- Alexander Y. Tetelbaum:
Path Search for Complicated Functions.
369-372
- Carsten F. Ball, Andreas Just, Dieter A. Mlynski:
A Fuzzy Mean Field Approach for Partitioning and Placement.
373-376
- Bernhard M. Riess, Gisela G. Ettelt:
Speed: Fast and Efficient Timing Driven Placement.
377-380
- Xiao Quan Li, Marwan A. Jabri:
Neural Network Based Estimation of VLSI Building Block Dimensions from Schematic.
381-384
- M. Kemal Unaltuna, Vijay Pitchumani:
ANSA: A New Neural Net Based Scheduling Algorithm for High Level Synthesis.
385-388
- Ian M. Bell, Kevin R. Eckersall, Stephen J. Spinks, Gaynor E. Taylor:
Fault Orientated Test and Fault Simulation of Mixed Signal Integrated Circuits.
389-392
- Jing-Jou Tang, Bin-Da Liu, Kuen-Jong Lee:
An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs).
393-396
VLSI Applications and Neural Networks
- Stefan Wolter, Holger Matz, Andreas Schubert, Rainer Laur:
On the VLSI Implementation of the International Data Encryption Algorithm IDEA.
397-400
- William A. Chren Jr.:
One-Hot Residue Coding for High-Speed Non-Uniform Pseudo-Random Test Pattern Generation.
401-404
- Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III:
High Speed, Fine Resolution Pattern Generation Using the Matched Delay Technique.
405-408
- Kuen-Jong Lee, Sheng-Yih Jeng, Tian-Pao Lee:
A New Architecture for Analog Boundary Scan.
409-412
- Jörg Kramer, Rahul Sarpeshkar, Christof Koch:
An Analog VLSI Velocity Sensor.
413-416
- M. Salerno, F. Sargeni, V. Bonaiuto:
DPCNN: A Modular Chip for Large CNN Arrays.
417-420
- Chua-Chin Wang, Jeng-Ming Wu:
Analysis and Current-Mode Implementation of Asymptotically Stable Exponential Bidirectional Associative Memory.
421-424
- Baoyun Wang, Luxi Yang, Hongtao Lu, Zhenya He:
On the Capacity of Intraconnected Bidirectional Associative Memory.
425-428
- Yoshihiko Horio, Ken Suyama:
Dynamic Associative Memory Using Switched-Capacitor Chaotic Neurons.
429-432
Video Coding and Processing
- Michael C. Doggett, Graham R. Hellestrand:
A Hardware Architecture for Video Rate Shading of Volume Data.
433-436
- Bin Fu, Keshab K. Parhi:
Generalized Multiplication Free Arithmetic Codes.
437-440
- Hugh Q. Cao, Weiping Li:
A New Multilevel Codebook Searching Algorithm for Vector Quantization.
441-444
- A. Nabout, Bing Su, H. A. Nour Eldin:
A Novel Closed Contour Extractor, Principle and Algorithm.
445-448
- Yui-Lam Chan, Wan-Chi Siu:
Fast Interframe Transfrom Coding Based on Characteristics of Transform Coefficients and Frame Difference.
449-452
- J. A. Provine, Leonard T. Bruton:
Lip Synchronization in 3-D Model Based Coding for Video-Conferencing.
453-456
- Touradj Ebrahimi, Homer H. Chen, Barry G. Haskell:
A Region Based Motion Compensated Video Codec for Very Low Bitrate Applications.
457-461
- Dong-il Chang, Young-kwon Cho, Souguil Ann:
A New Wavelet Tranform-Based CELP Coder with Band Selection and Selective VQ.
462-465
- Keith Hung-Kei Chow, Ming L. Liou:
Simple Cell Admission Control and Buffer Management Scheme for Mulitclass Video-On-Demand Service.
466-469
- R. K. Bertschmann, N. R. Bartley, Leonard T. Bruton:
A 3-D Integrator-Differentiator Double-Loop (IDD) Filter for Raster-Scan Video Processing.
470-473
Neural Network Theory
- Raffaele Parisi, Elio D. Di Claudio, Gianni Orlandi:
Total Least Squares Approach for Fast Learning in Multilayer Neural Networks.
474-477
- Wu Meng, Feng Guangzeng:
A Multi-Solution Learning Algorithm for Fuzzy Rules.
478-481
- Yoshikazu Miyanaga, Honglan Jin, Rafiqul Islam, Koji Tochinai:
A Self-Organized Network with a Supervised Training.
482-485
- Jun Wang, Ce Zhu, Chenwu Wu, Zhenya He:
Neural Network Approaches to fast and Low Rate Vector Quantization.
486-489
- Aijit Dingankar, Irwin W. Sandberg:
On Error Bounds for Neural Network Approximation.
490-492
- Takeshi Kamio, Hiroshi Ninomiya, Hideki Asai:
Convergence of Hopfield Neural Network for Orthogonal Transformation.
493-496
- Tzuu-Hseng S. Li, Chyi-Cherng Lai:
Lyapunov Function Based Fuzzy State Estimator.
497-500
- Mark P. Joy, Vedat Tavsanoglu:
Circulant Matrices and the Stability of Ring CNNs.
501-504
- Paolo Arena, Luigi Fortuna, Giovanni Muscato, Maria Gabriella Xibilia:
Fast Learning by Weight Estimation in Complex Valued MLPs.
505-508
Combinatronics in Advanced CAS II
- Morikazu Nakamura, Kenji Onaga, Seiki Kyan, Manuel Silva:
A Genetic Algorithm for Sex-Fair Stable Marriage Problem.
509-512
- Masato Nakagawa, Dong-Ik Lee, Sadatoshi Kumagai, Shinzo Kodama:
Equivalent Net Abstraction and Firing Sequence Preservation.
513-516
- Tadao Murata, Jaegeol Yim:
Petri-Net Methods for Reasoning in Real-Time Control Systems.
517-520
- Atsushi Togashi, Nobuyuki Usui, Kukhwan Song, Norio Shiratori:
A Derivation of System Specifications Based on a Partial Logical Petri Net.
521-524
Analog-To-Digital Converters I
- João Goes, João C. Vital, José E. Franca:
Optimum Resolution-per-Stage in High-Speed Pipelined A/D Converters Using Self-Calibration.
525-528
- Jorge Guilherme, José E. Franca:
New CMOS Logarithmic A/D Converters Employing Pipeline and Algorithmic Architectures.
529-532
- Zheng Tang, Yuichi Shirata, Okihiko Ishizuka, Koichi Tanno:
A Self-Calibrating A/D Converter Using T-Model Neural Network.
533-536
- Chih-Cheng Chen, Chung-Yu Wu, Jyh-Jer Cho:
A 1.5 V CMOS Current-Mode Cyclic Analog-to-Digital Converter with Digital Error Correction.
537-540
- A. Häberli, Piero Malcovati, Henry Baltes, Franco Maloberti:
An Incremental A/C Converter for Accurate Vector Probe Measurements.
541-544
VLSI DSP I
Timing Simulation
Filter Banks and Multirate Processing I
Motion Compensated Block-Based Video Compression I
- Jian Feng, Hassan Mehrpour, Kwok-Tung Lo, A. E. Karbowiak:
Two-Layer MPEG Video Coding Algorithm for ATM Networks.
605-608
- Marco Winzker, Peter Pirsch, Jochen Reimers:
Architecture and Memory Requirements for Stand-Alone and Hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMs.
609-612
- Yanghoon Kim, Chong S. Rim, Byoungki Min:
A Block Matching Algorithm with 16: 1 Subsampling and Its Hardware Design.
613-616
- Michael C. Chen, Alan N. Willson Jr.:
A High Accuracy Predictive Logarithmic Motion Estimation Algorithm for Video Coding.
617-620
- Stefan Honken, Feng-Ming Yang, Rainer Laur:
A HDTV-Suited Architecture for a Fast Full Search Block-Matching Algorithm.
621-624
Mathematical Treatment of Delta-Sigma Modulators
Theory and Implementation of Cellular Neural Networks
Circuit Theory Approach to Mechatronics I
Synchronization and Control of Chaotic Systems I
Analog-to-Digital Converters II
VLSI DSP II
Circuit Simulation
Filter Banks and Multirate Processing II
Motion Compensated Block-Based Video Coding II
Copyright © Mon Nov 2 20:52:26 2009
by Michael Ley (ley@uni-trier.de)
