ICPP 1985:
University Park,
PA,
USA
International Conference on Parallel Processing (ICPP '85),
University Park,
PA,
USA,
August 1985. IEEE Computer Society Press,
1985
Session 1a:
Parallel Algorithms -I
Session 1b:
Vector/Array Processing
- Eugene D. Brooks III:
Performance of the Butterfly Processor-Memory Interconnection in a Vector Environment.
21-24
- Daniel A. Reed, Merrell L. Patrick:
Iterative Solution of Large, Sparse, Linear Systems on a Static Data Flow Architecture: Performance Studies.
25-32
- Wilfried Oed, Otto Lange:
On the Effective Bandwidth of Interleaved Memories in Vector Processor Systems.
33-40
- Abhiram G. Ranade:
Interconnection Networks And Parallel Memory Organizations For Array Processing.
41-47
Session 1c:
Problem Mapping and Scheduling
Session 2a:
Parallel Architectures
Session 2b:
Systolic Systems
Session 2c:
Logic Programming
Session 3a:
Operating System Problems
Session 3b:
Parallel Algorithms/ Simulation
Session 3c:
Parallel Computation
Session 4a:
languages for Parallel Processing
Session 4b:
Memory Management
Session 4c:
Numeric Processing
Session 5a:
Interconnection Networks - I
Session 5b:
Data Flow
Session 5c:
Parallel Algiorithms
Session 6a:
Interconnection Networks
Session 6b:
Numeric Computing
Session 6c:
Parallel Programming
Session 7a:
Network Performance
Session 7b:
Aspects of Parallel Systems
Session 7c:
Data Flow -II
Session 8a:
Performance Measurement
Session 8b:
Logic Programming / Production Systems
Session 8c:
Parallel Systems - II
Session 9a:
Expressing Parallelism
Session 9b:
Parallell Systems - II
- Jouko O. Viitanen, Pertti Vanni:
The TAMIPS Multiprocessor.
643-645
- Michel Dubois:
A Cache-Based Multiprocessor with High Efficiency.
646-648
- Lee D. Coraor, Paul T. Hulina:
A Reconfigurable Multiprocessor.
649-651
- Wolfgang Händler, Erik Maehle, Klaus Wirl:
Dirmu Multiprocessor Configurations.
652-656
- Ping-Sheng Tseng, Kai Hwang, Viktor K. Prasanna:
A VLSI-Based Multiprocessor Architecture for Implementing Parallel Algorithms.
657-664
- James C. Browne:
Characterization of Parallel Architecture.
665
- Jesus O. Tuazon, John C. Peterson, Moshe Pniel, Don Lieberman:
Caltech/JPL MARK II Hypercube Concurrent Processor.
666-673
- Ran Ginosar, Dwight D. Hill:
Design and Implementation of Switching Systems for Parallel Processors.
674-680
- Creve Maples:
Pyramids, Crossbars and Thousands of Processors.
681-688
- William Robertson, D. Pincock, D. N. Swingler:
A Reconfigurable Architecture for Digital Time Domain Beamforming.
689-696
Session 10a:
Mesh-Structured Systems
Session 10b:
Problem Mapping Techniques
Session 10c:
Systolic Systems
Session 11a:
The IBM Research Parallel Processor
- Gregory F. Pfister, William C. Brantley, David A. George, Steve L. Harvey, Wally J. Kleinfelder, Kevin P. McAuliffe, Evelin S. Melton, V. Alan Norton, Jodi Weiss:
The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture.
764-771
- V. Alan Norton, Gregory F. Pfister:
A Methodology for Predicting Multiprocessor Performance.
772-781
- William C. Brantley, Kevin P. McAuliffe, Jodi Weiss:
RP3 Processor-Memory Element.
782-789
- Gregory F. Pfister, V. Alan Norton:
"Hot Spot" Contention and Combining in Multistage Interconnection Networks.
790-797
Session 11b:
Fault Tolerance and Reliability
Session 12a:
Functional / Numeric Programming
Session 12b:
Sorting
Copyright © Mon Nov 2 20:47:02 2009
by Michael Ley (ley@uni-trier.de)
