ICCD 2007: Lake Tahoe, CA, USA

Signal Processing Circuits

• In-Cheol Park, WonHee Son, Ji-Hoon Kim:
  Twiddle factor transformation for pipelined FFT processing. 1-6
  
• Hani Saleh, Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.:
  Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine. 7-12
  
• Santosh Ghosh, Avishek Saha:
  Speed-area optimized FPGA implementation for Full Search Block Matching. 13-18
  

Advances in Verification

• Nannan He, Michael S. Hsiao:
  Bounded model checking of embedded software in wireless cognitive radio systems. 19-24
  
• Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
  Application of symbolic computer algebra to arithmetic circuit verification. 25-32
  
• Jae W. Lee, Myron King, Krste Asanovic:
  Continual hashing for efficient fine-grain state inconsistency detection. 33-40
  
• Lochi Lo Chi Yu Lo, Samar Abdi:
  Automatic SystemC TLM generation for custom communication platforms. 41-46
  

Novel Memory and Communication Subsystems

• Subramanian Ramaswamy, Sudhakar Yalamanchili:
  Improving cache efficiency via resizing + remapping. 47-54
  
• Li Zhao, Ravi R. Iyer, Ramesh Illikkal, Donald Newell:
  Exploring DRAM cache architectures for CMP server platforms. 55-62
  
• Amit Kumar, Partha Kundu, Arvind P. Singh, Li-Shiuan Peh, Niraj K. Jha:
  A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS. 63-70
  

Variation Aware Design Methodologies

• Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu:
  Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. 71-77
  
• Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan:
  Voltage drop reduction for on-chip power delivery considering leakage current variations. 78-83
  
• Aswin Sreedhar, Sandip Kundu:
  On modeling impact of sub-wavelength lithography on transistors. 84-90
  
• Cristiano Forzan, Davide Pandini:
  Why we need statistical static timing analysis. 91-96
  
• Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak:
  Statistical timing analysis using Kernel smoothing. 97-102
  

Tutorial: Software-Defined Radio (SDR) Technology

• Mark Cummings, Todor Cooklev:
  Tutorial: Software-defined radio technology. 103-104
  

Microarchitecture, Multiprocessors and Systems-on-chip

• Erika Gunadi, Mikko H. Lipasti:
  A position-insensitive finished store buffer. 105-112
  
• Austin Rogers, Milena Milenkovic, Aleksandar Milenkovic:
  A low overhead hardware technique for software integrity and confidentiality. 113-120
  
• Manoj Gupta, Fermín Sánchez, Josep Llosa:
  Cluster-level simultaneous multithreading for VLIW processors. 121-128
  
• Abhishek Das, Serkan Ozdemir, Gokhan Memik, Alok N. Choudhary:
  Evaluating voltage islands in CMPs under process variations. 129-136
  

FPGA Architecture and Design

• Michael T. Frederick, Arun K. Somani:
  Non-arithmetic carry chains for reconfigurable fabrics. 137-143
  
• Yuanfang Hu, Yi Zhu, Michael Bedford Taylor, Chung-Kuan Cheng:
  FPGA global routing architecture optimization using a multicommodity flow approach. 144-151
  
• Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan:
  FPGA routing architecture analysis under variations. 152-157
  
• Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Sudarshan Banerjee:
  Energy-aware co-processor selection for embedded processors on FPGAs. 158-163
  

Application-Optimized Architectures

• Liang-Kai Wang, Charles Tsen, Michael J. Schulte, Divya Jhalani:
  Benchmarks and performance analysis of decimal floating-point applications. 164-170
  
• Yoshiyuki Kaeriyama, Daichi Zaitsu, Ken-ichi Suzuki, Hiroaki Kobayashi, Nobuyuki Ohba:
  Multi-core data streaming architecture for ray tracing. 171-178
  
• David Meisner, Sherief Reda:
  Hardware libraries: An architecture for economic acceleration in soft multi-core environments. 179-186
  
• Hai Lin, Xuan Guan, Yunsi Fei, Zhijie Jerry Shi:
  Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors. 187-193
  

Three-Dimensional Integrated Circuits

• Lili Zhou, Cherry Wakayama, Robin Panda, Nuttorn Jangkrajarng, Bo Hu, C.-J. Richard Shi:
  Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits. 194-201
  
• Phil Jacobs, Aamir Zia, Okan Erdogan, Paul M. Belemjian, Peng Jin, Jin Woo Kim, Michael Chu, Russell P. Kraft, John F. McDonald:
  Amdahl's figure of merit, SiGe HBT BiCMOS, and 3D chip stacking. 202-207
  
• Xiaoxia Wu, Paul Falkenstern, Yuan Xie:
  Scan chain design for three-dimensional integrated circuits (3D ICs). 208-214
  

Industry Challenges in Wireless Communication

• Ulrich Ramacher:
  Challenges and prospects of SDR for mobile phones. 215
  
• Karsten Vandrup:
  The challenge in testing MIMO in a Wi-Fi or WiMAX context. 215
  

Cache memory architecture (I)

• Hyunjin Lee, Sangyeun Cho, Bruce R. Childers:
  Exploring the interplay of yield, area, and performance in processor caches. 216-223
  
• Koustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan:
  Improving the reliability of on-chip L2 cache using redundancy. 224-229
  
• Houman Homayoun, Alexander V. Veidenbaum:
  Reducing leakage power in peripheral circuits of L2 caches. 230-237
  
• Fei Gao, Hanyu Cui, Suleyman Sair:
  Two-level ata prefetching. 238-244
  
• Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras:
  Cache replacement based on reuse-distance prediction. 245-250
  

Novel Techniques in Physical Design

• Huan Ren, Shantanu Dutt:
  Constraint satisfaction in incremental placement with application to performance optimization under power constraints. 251-258
  
• Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, Jason Cong:
  Fine grain 3D integration for microarchitecture design through cube packing exploration. 259-266
  
• Eric Wong, Sung Kyu Lim:
  Whitespace redistribution for thermal via insertion in 3D stacked ICs. 267-272
  
• Mohit Pathak, Souvik Mukherjee, Madhavan Swaminathan, Ege Engin, Sung Kyu Lim:
  Placement and routing of RF embedded passive designs in LCP substrate. 273-279
  

Arithmetic Circuits

• Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi:
  A radix-10 SRT divider based on alternative BCD codings. 280-287
  
• Charles Tsen, Sonia Gonzalez-Navarro, Michael J. Schulte:
  Hardware design of a Binary Integer Decimal-based floating-point adder. 288-295
  
• Brian J. Hickmann, Andrew Krioukov, Michael J. Schulte, Mark A. Erle:
  A parallel IEEE P754 decimal floating-point multiplier. 296-303
  
• Michael J. Schulte, Dimitri Tan, Carl Lemonds:
  Floating-point division algorithms for an x86 microprocessor with a rectangular multiplier. 304-310
  
• Gongqiong Li, Zhaolin Li:
  Optimized design of a double-precision floating-point multiply-add-dused unit for data dependence. 311-316
  

Reliability and fault tolerance

• Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz:
  Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor. 317-324
  
• Wei Wu, Sheldon X.-D. Tan, Jun Yang, Shih-Lien Lu:
  Improving the reliability of on-chip data caches under process variations. 325-332
  
• Joonhyuk Yoo, Manoj Franklin:
  Prioritizing verification via value-based correctness criticality. 333-340
  
• Somnath Paul, Swarup Bhunia:
  Memory based computation using embedded cache for processor yield and reliability improvement. 341-346
  

Novel Test Techniques

• Hugo Cheung, Sandeep K. Gupta:
  Accurate modeling and fault simulation of Byzantine resistive bridges. 347-353
  
• Jie Li, John Lach:
  Negative-skewed shadow registers for at-speed delay variation characterization. 354-359
  
• Jianxun Liu, Wen-Ben Jone:
  An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects. 360-367
  
• Siavash Bayat Sarmadi, M. Anwar Hasan:
  Detecting errors in a polynomial basis multiplier using multiple parity bits for both inputs. 368-375
  
• Chong Zhao, Sujit Dey:
  Modeling soft error effects considering process variations. 376-381
  

Low Power Design

• Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki:
  An automated runtime power-gating scheme. 382-387
  
• Ku He, Rong Luo, Yu Wang:
  A power gating scheme for ground bounce reduction during mode transition. 388-394
  
• Yoonjin Kim, Rabi N. Mahapatra:
  Dynamically compressible context architecture for low power coarse-grained reconfigurable array. 395-400
  
• Sheng Sun, Carl Sechen:
  Post-layout comparison of high performance 64b static adders in energy-delay space. 401-408
  

Power and thermal considerations in processor design

• James Tuck, Wei Liu, Josep Torrellas:
  CAP: Criticality analysis for power-efficient speculative multithreading. 409-416
  
• Mehdi Modarressi, Hamid Sarbazi-Azad:
  Power-aware mapping for reconfigurable NoC architectures. 417-422
  
• Jugash Chandarlapati, Mainak Chaudhuri:
  LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation. 423-430
  
• Raid Ayoub, Alex Orailoglu:
  Power efficient register file update approach for embedded processors. 431-437
  

Circuit Design and Simulation

• Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen:
  A technique for selecting CMOS transistor orders. 438-443
  
• Veerapaneni Nagbhushan, C. Y. Roger Chen:
  Algorithms to simplify multi-clock/edge timing constraints. 444-449
  
• Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen:
  An efficient gate delay model for VLSI design. 450-455
  
• Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng:
  Fast power network analysis with multiple clock domains. 456-463
  

Simulation and Scheduling

• Davy Genbrugge, Lieven Eeckhout:
  Statistical simulation of chip multiprocessors running multi-program workloads. 464-471
  
• Paul D. Bryan, Thomas M. Conte:
  Combining cluster sampling with single pass methods for efficient sampling regimen design. 472-479
  
• Xiang Xiao, Jaehwan John Lee:
  A novel O(1) parallel deadlock detection algorithm and architecture for multi-unit resource systems. 480-487
  

Cache memory architecture

• Mohammad A. Makhzan, Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi:
  Limits on voltage scaling for caches utilizing fault tolerant techniques. 488-495
  
• Weng-Fai Wong, Cheng-Kok Koh, Yiran Chen, Hai Li:
  VOSCH: Voltage scaled cache hierarchies. 496-503
  
• Valentina Salapura, José R. Brunheroto, Fernando F. Redigolo, Alan Gara:
  Exploiting eDRAM bandwidth with data prefetching: simulation and measurements. 504-511
  

RF and Analog Test

• Erkan Acar, Sule Ozev:
  Digital calibration of RF transceivers for I-Q imbalances and nonlinearity. 512-517
  
• Selim Sermet Akbay, Abhijit Chatterjee:
  Fault-based alternate test of RF components. 518-525
  
• Mingjing Chen, Alex Orailoglu:
  Circuit-level mismatch modelling and yield optimization for CMOS analog circuits. 526-532
  

Synchronization and Interconnect

• Niklas Lotze, Maurits Ortmanns, Yiannos Manoli:
  A Study on self-timed asynchronous subthreshold logic. 533-540
  
• Julian J. H. Pontes, Rafael Soares, Ewerson Carvalho, Fernando Moraes, Ney Calazans:
  SCAFFI: An intrachip FPGA asynchronous interface based on hard macros. 541-546
  
• Chun-Chen Liu, Haikun Zhu, Chung-Kuan Cheng:
  Passive compensation for high performance inter-chip communication. 547-552
  
• Eric L. Hill, Mikko H. Lipasti:
  Transparent mode flip-flops for collapsible pipelines. 553-560
  

Design Techniques for Emerging Technologies

• Anish Muttreja, Niket Agarwal, Niraj K. Jha:
  CMOS logic design with independent-gate FinFETs. 560-567
  
• Ali Namazi, Mehrdad Nourani:
  Distributed voting for fault-tolerant nanoscale systems. 568-573
  
• Shu Li, Tong Zhang:
  Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits. 574-579
  
• Rajarajan Senguttuvan, Shreyas Sen, Abhijit Chatterjee:
  VIZOR: Virtually zero margin adaptive RF for ultra low power wireless communication. 580-586
  

System Level and Architectural Synthesis

• Noureddine Chabini, Wayne Wolf:
  Register binding guided by the size of variables. 587-594
  
• Balasubramanian Sethuraman, Ranga Vemuri:
  Power variations of multi-port routers in an application-specific NoC design : A case study. 595-600
  
• Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt:
  System level power estimation methodology with H.264 decoder prediction IP case study. 601-608
  
• Bita Gorjiara, Daniel Gajski:
  A novel profile-driven technique for simultaneous power and code-size optimization of microcoded IPs. 609-614
  

Process-aware Design: Power, Thermal and Reliability

• Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya:
  Power reduction of chip multi-processors using shared resource control cooperating with DVFS. 615-622
  
• Inchoon Yeo, Heung Ki Lee, Eun Jung Kim, Ki Hwan Yum:
  Effective Dynamic Thermal Management for MPEG-4 decoding. 623-628
  
• Dakai Zhu, Xuan Qi, Hakan Aydin:
  Priority-monotonic energy management for real-time systems with reliability requirements. 629-635
  
• Ming Su, Lili Zhou, C.-J. Richard Shi:
  Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining. 636-643