ICCD 1993: Cambridge, MA, USA

Concurrent Plenary Sessions 1.2.1

CAD Plenary

• Randal E. Bryant: Symbolic Analysis Methods for Masks, Circuits, and Systems. 6-8

Concurrent Plenary Sessions 1.2.2

Embedded Systems Plenary

• Daniel P. Siewiorek: Wearable Computers: Merging Information Space with the Workspace. 10-11

Design and Test Plenary

• Thomas W. Williams: Design for Testability: Today and in the Future. 14

Concurrent Sessions 1.3

Estimation Techniques for Global Optimization in High-Level Synthesis

• Michel Langevin, Eduard Cerny: A Recursive Technique for Computing Lower-Bound Performance of Schedules. 16-20
• Yuan Hu, Ahmed Ghouse, Bradley S. Carlson: Lower Bounds on the Iteration Time and the Number of Resources for Functional Pipelined Data Flow Graphs. 21-24
• Samit Chaudhuri, Robert A. Walker, John Mitchell: The Structure of Assignment, Precedence, and Resource Constraints in the ILP Approach to the Scheduling Problem. 25-29

Cache Architectures

• Rodney Boleyn, James Debardelaben, Vivek Tiwari, Andrew Wolfe: A Split Data Cache for Superscalar Processors. 32-39
• André Seznec: About Set and Skewed Associativity on Second-Level Caches. 40-43
• Honesty C. Young, Eugene J. Shekita: An Intelligent I-Cache Prefetch Mechanism. 44-49

Design Verification and Modification

• Pinhong Chen, Jyuo-Min Shyu, Liang-Gee Chen: Hardware Verification Using Symbolic State Transition Graphs. 54-57
• Sofiène Tahar, Ramayya Kumar: Towards a Methodology for the Formal Hierarchical Verification. 58-62
• Praveen Vishakantaiah, Thomas Thomas, Jacob A. Abraham, Magdy S. Abadir: AMBIANT: Automatic Generation of Behavioral Modifications for Testability. 63-66

Concurrent Sessions 1.4

Timing Anlaysis and Optimization

• João P. Marques Silva, Karem A. Sakallah: An Analysis of Path Sensitization Criteria. 68-72
• Hsi-Chuan Chen, Siu-Wing Cheng, Yaun-Chung Hsu, David Hung-Chang Du: A Path Sensitization Approach to Area Reduction. 73-76
• Horng-Fei Jyu, Sharad Malik: Statistical Timing Optimization of Combinatorial Logic Circuits. 77-80
• Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins: Fidelity and Near-Optimality of Elmore-Based Routing Constructions. 81-84

High Performance General Purpose Machines

• Trung A. Diep, Mikko H. Lipasti, John Paul Shen: Architecture-Compatible Code Boosting for Performance Enhancement of the IBM RS/6000. 86-93
• Thomas M. Conte, William H. Mangione-Smith: Determining Cost-Effective Multiple Issue Processor Designs. 94-101
• Chia-Jiu Wang, Frank Emnett: Area and Performance Comparison of Pipelined RISC Processors Implementing Different Precise Interrupt Methods. 102-105
• Hideki Ando, Chikako Nakanishi, Hirohisa Machida, Tetsuya Hara, Satoru Kishida, Masao Nakaya: Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine. 106-113

Embedded System Architectures

• Raymond Roth, John Watkins, Michael Hsieh, William Radke, Donald Hejna, Richard Tom, Byung Kim: An Integrated Environment for Concurrent Development of a Pixel Processor ASIC and Application Software. 116-125
• Ulrich Holtmann, Rolf Ernst: Speculative Computation for Coprocessor Synthesis. 126-131
• J. Morris Chang, Edward F. Gehringer: Evaluation of an Object-Caching Coprocessor Design for Object-Oriented Systems. 132-139
• Wayne Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems: The Spring Scheduling Co-Processor: A Scheduling Accelerator. 140-144

Scan Design

• Scott Chiu, Christos A. Papachristou: A Partial Scan Cost Estimation Method at the System Level. 146-150
• Sandeep Bhatia, Niraj K. Jha: Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan. 151-154
• Xiaodong Xie, Alexander Albicki: Bit-Splitting for Testability Enhancement in Scan-Based Design. 155-158
• Chin-Long Wey, Ming-Der Shieh, P. David Fisher: ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits. 159-162

Concurrent Sessions 2.1

Asynchronous Design

• Tod Amon, Henrik Hulgaard, Steven M. Burns, Gaetano Borriello: An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems. 166-173
• Enric Pastor, Jordi Cortadella: An Efficient Unique State Coding Algorithm for Signal Transition Graphs. 174-177
• Richard Auletta, Robert B. Reese, Cherrice Traver: A Comparison of Synchronous and Asynchronous FSMD Designs. 178-182

Desgin Concepts

• N. Ranganathan, Raghu Sastry, R. Venkatesan, Joseph W. Yoder, David C. Keezer: SMAC: A Scene Matching Chip. 184-187
• Ted Kehl: Hardware Self-Tuning and Circuit Performance Monitoring. 188-192
• Jien-Chung Lo: Fault-Tolerant Content Addressable Memory. 193-196

Multipliers/Dividers

• Debabrata Ghosh, S. K. Nandy: A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology. 198-201
• Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara: A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture. 202-205
• Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi: A C-Testable Carry-Free Divider. 206-213

Programmable Gate Array Architectures and Systems

• Telle Whitney, Jeff Schlageter: A New High Performance Field Programmable Gate Array Family. 216-219
• Kaushik Roy, Sudip Nag, Santanu Dutta: Channel Architecture Optimization for Performance and Routability of Row-Based FPGAs. 220-223
• Jagannathan Narasimhan, Kazuo Nakajima: A Reconfiguration-Based Yield Enhancement System. 224-228

Concurrent Sessions 2.2

Formal Methods I

• C. Norris Ip, David L. Dill: Efficient Verification of Symmetric Concurrent Systems. 230-234
• P. A. Subrahmanyam, Josep M. Espinalt, Meng-Lin Yu: Specification and Synthesis of Mixed-Mode Systems: Experiments in a VHDL Environment. 235-241
• Masahiro Fujita, Shinji Kono: Synthesis of Controllers from Interval Temporal Logic Specification. 242-245

Microprocessor Design

• Timothy B. Brodnax, Mike Schiffli, Floyd Watson: The PowerPC 601 Design Methodology. 248-252
• Susumu Narita, Fumio Arakawa, Kunio Uchiyama, Ikuya Kawasaki: Design Methodology for GMICRO^TM/500 TRON Microprocessor. 253-257
• Avtar Saini: Design of the Intel Pentium^TM Processor. 258-261

Computer Arithmetic

• Ali Skaf, Alain Guyot: VLSI Design of On-Line Add/Multiply Algorithms. 264-267
• Gong Guo, Mohammad Ashtijou: A Note About the Correction Cycle of High Radix Booth's Multiplication. 268-271
• Dhananjay S. Phatak, Israel Koren, Hoon Choi: Hybrid Number Representations with Bounded Carry Propagation Chains. 272-275

VLSI Systems

• Toshikazu Sakano, Takao Matsumoto, Kazuhiro Noguchi: A Three-Dimensional Mesh Multiprocessor System Using Board-to-Board Free-Space Optical Interconnects: COSINE-III. 278-283
• Tzi-cker Chiueh: A Vector Memory System Based on Wafer-Scale Integrated Memory Arrays. 284-288
• K. Ishibashi, T. Hayashi, T. Doi, N. Masuda, A. Yamagiwa, T. Okabe: A Novel Clock Distribution System for CMOS VLSI. 289-292

Concurrent Sessions 2.3

Binary Decision Diagrams

• Jaehong Park, M. Ray Mercer: An Efficient Symbolic Design Verification System. 294-298
• Gianpiero Cabodi, Paolo Camurati: Exploiting Cofactoring for Efficient FSM Symbolic Traversal Based on the Transition Relation. 299-303
• Prabhat Jain, Ganesh Gopalakrishnan: Hierarchical Constraint Solving in the Parametric Form with Applications to Efficient Symbolic Simulation Based Verification. 304-307

Test Generation and Evaluation

• Weidong Li, Carl McCrosky, Mostafa H. Abd-El-Barr: Reducing the Cost of Test Pattern Generation by Information Reusing. 310-313
• Rathish Jayabharathi, Thomas Thomas, Earl E. Swartzlander Jr.: A Comparative Evaluation of Adders Based on Performance and Testability. 314-317
• Ravindranath Naiknaware: Analog Automatic Test Plan Generator - Integrating with Modular Analog IC Design Environment. 318-321

Memory Systems

• John Watkins, Raymond Roth, Michael Hsieh, William Radke, Donald Hejna, Byung Kim, Richard Tom: A Memory Controller with an Integrated Graphics Processor. 324-338
• Tzi-cker Chiueh: Trail: A Track-Based Logging Disk Architecture for Zero-Overhead Writes. 339-343
• Lishing Liu: Multiple-Page Translation for TLB. 344-349

Analysis and Simulation

• Perng-Shyong Lin, Charles A. Zukowski: Analysis and Control of Timing Jitter in Digital Logic Arising from Noise Voltage Sources. 352-356
• Anirudh Devgan, Ronald A. Rohrer: ACES: A Transient Simulation Strategy for Integrated Circuits. 357-360
• Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown: Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation. 361-364

Concurrent Sessions 2.4

Scheduling Techniques in High-Level Synthesis

• Ti-Yen Yen, Wayne Wolf: Optimal Scheduling of Finite-State Machines. 366-369
• Usha Prabhu, Barry M. Pangrle: Global Mobility Based Scheduling. 370-373
• Ching-Tang Chang, Kenneth Rose, Robert A. Walker: Cluster-Oriented Scheduling in Pipelined Data Path Syntesis. 374-378
• Jer-Min Jou, Shiann-Rong Kuang: Library-Adaptively Integrated Data Path Synthesis for DSP Systems. 379-382

Economics of Design and Test

• Chryssa Dislis, Anthony P. Ambler, I. D. Dear, J. H. Dick: Economics in Design and Test. 384-387
• B. R. Wilkins, C. Shi: Design Guidelines and Testability Assessment. 388-391

Fine Grain Parallelism

• Yusuke Mishina, Keiji Kojima: String Matching on IDP: A String Matching Algorithm for Vector Processors and Its Implementation. 394-401
• Raghu Sastry, N. Ranganathan: A Systolic Array for Approximate String Matching. 402-405
• Alex G. Dickinson, C. J. Nicol: A Systolic Architecture for High Speed Pipelined Memories. 406-409
• D. Scott Wills, W. Stephen Lacy, Huy Cat, Michael A. Hopper, Ashutosh Razdan, Sek M. Chai: Pica: An Ultra-Light Processor for High-Througput Applications. 410-414

Combinatorial Logic Optimization

• Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton: Logic Optimization with Multi-Output Gates. 416-420
• Bill Lin, Hugo De Man: Low-Power Driven Technology Mapping under Timing Constraints. 421-427
• Vigyan Singhal, Yosinori Watanabe, Robert K. Brayton: Heuristic Minimization of Synchronous Relations. 428-433

Concurrent Sessions 3.1

Formal Methods II

• Kamlesh Rath, Bhaskar Bose, Steven D. Johnson: Derivation of a DRAM Memory Interface by Sequential Decomposition. 438-441
• Paul R. Stephan, Robert K. Brayton: Physically Realizable Gate Models. 442-445
• Xin Hua, Hantao Zhang: Formal Semantics of VHDL for Verification of Circuit Designs. 446-449

Partitioning and Analysis

• W. Ye, Rolf Ernst, Thomas Benner, Jörg Henkel: Fast Timing Analysis for Hardware-Software Co-Synthesis. 452-457
• Bhaskar Bose, M. Esen Tuna, Steven D. Johnson: System Factorization in Codesign: A Case Study of the Use of Formal Techniques to Achieve Hardware-Software Decomposition. 458-461
• K. ten Hagen, Heinrich Meyr: Partitioning and Surmounting the Software-Hardware Abstraction Gap in an ASIC Design Project. 462-465

Methods and Limitations in CAD Layout

• Wing Ning Li: Strongly NP-Hard Discrete Gate Sizing Problems. 468-471
• Jeffrey S. Salowe, David M. Warme: An Exact Rectilinear Steiner Tree Algorithm. 472-475
• Dian Zhou, F. Tsui: Neighbour State Transition Method for VLSI Optimization Problems. 476-479

FPGAs for Custom Computing Machines

• Jeffrey M. Arnold, Duncan A. Buell, Dzung T. Hoang, Daniel V. Pryor, Nabeel Shirazi, Mark R. Thistle: The Splash 2 Processor and Applications. 482-485
• Christian Iseli, Eduardo Sanchez: Beyond Superscalar Using FPGAs. 486-490
• David M. Lewis, Marcus van Ierssel, Daniel H. Wong: A Field Programmable Accelerator for Compiled-Code Applications. 491-496

Concurrent Sessions 3.2

Logic Synthesis

• Miodrag Potkonjak, Sujit Dey, Zia Iqbal, Alice C. Parker: High Performance Embedded System Optimization Using Algebraic and Generalized Retiming Techniques. 498-504
• Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Some Results on the Complexity of Boolean Functions for Table Look Up Architectures. 505-512
• Bill Lin: Efficient Symbolic Support Manipulation. 513-516

Design for Testability

• Jayashree Saxena, Dhiraj K. Pradhan: Desgin for Testability of Asynchronous Sequential Circuits. 518-522
• Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia: Pseudoexhaustive BIST for Sequential Circuits. 523-527
• Alex Orailoglu, Ian G. Harris: Test Path Generation and Test Scheduling for Self-Testable Designs. 528-531

Reliability Issues

• Ping-Chung Li, Ibrahim N. Hajj: Computer-Aided Redesign of VLSI Circuits for Hot-Carrier Reliability. 534-537
• Hungse Cha, Janak H. Patel: A Logic-Level Model for alpha-Paricle Hits in CMOS Circuits. 538-542
• Ronald D. Hindmarsh: Complex Gate Performance Improvement by Jog Insertion into Transistor Gates. 543-546

High Level Tools

• Mark Aagaard, Miriam Leeser: A Framework for Specifying and Designing Pipelines. 548-551
• Todd A. Cook, Paul D. Franzon, Edwin A. Harcourt, Thomas K. Miller III: System-Level Specification of Instruction Sets. 552-557
• Lyle D. Kipp, David J. Kuck: Newton: Performance Improvement Through Comparative Analysis. 558-561

Concurrent Sessions 3.3

Fault Simulation

• Shang-E Tai, Debashis Bhattacharya: Pipelined Fault Simulation on Parallel Machines Using the Circuit Flow Graph. 564-567
• Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham: MIXER: Mixed-Signal Fault Simulator. 568-571
• Giacomo Buonanno, Franco Fummi, Donatella Sciuto: Functional Fault Models and Gate Level Coverage for Sequential Architectures. 572-575
• Laura Farinetti, Pier Luca Montessoro: An Adaptive Technique for Dynamic Rollback in Concurrent Event-Driven Fault Simulation. 576-582

Fault Tolerance and Reliability

• Régis Leveugle, X. Delord, Gabriele Saucier: Influence of Error Correlations on the Signature Analysis Aliasing. 584-587
• Rajiv Gupta: Phi-Test: Perfect Hashed Index Test for Test Response Validation. 588-591
• Santhanam Srinivasan, Niraj K. Jha: Efficient Diagnosis in Algorithm-Based Fault Tolerant Multiprocessor Systems. 592-595
• F. L. Vargas, Michael Nicolaidis, Bernard Courtois: Quiescent Current Monitoring to Improve the Reliability of Electronic Systems in Space Radiation Environments. 596-600

Signal Processing

• René J. Glaise, X. Jacquart: Fast CRC Calculation. 602-605
• Abhijit Chatterjee, Rabindra K. Roy: Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive Filters. 606-609
• Luc J. M. Claesen, Joan Daemen, Mark Genoe, G. Peeters: Subterranean: A 600 Mbit/Sec Cryptographic VLSI Chip. 610-613
• Artur Wrzyszcz, David Milford: A New Modulo 2^a + 1 Multiplier. 614-617