USA Georges G. E. Gielen (Ed.):
2007 International Conference on Computer-Aided Design (ICCAD'07), November 5-8, 2007, San Jose, CA, USA.
IEEE 2007, ISBN 1-4244-1382-6
Advances in parasitic extraction and variability modeling
Networks-on-Chip and latency-insensitive systems
Power grid analysis
- Imad A. Ferzli, Farid N. Najm, Lars Kruse:
A geometric approach for early power grid verification using current constraints.
- Ning Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong:
Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks.
- Kai Sun, Quming Zhou, Kartik Mohanram, Danny C. Sorensen:
Parallel domain decomposition for simulation of large-scale power grids.
Synthesis and verification of quantum circuits
Connecting physical challenges and design approaches
Analytical techniques for physical optimization
Memory optimization and system-level timing
- Mahmut T. Kandemir:
Data locality enhancement for CMPs.
- Ilie I. Luican, Hongwei Zhu, Florin Balasa:
Mapping model with inter-array memory sharing for multidimensional signal processing.
- Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Increasing data-bandwidth to instruction-set extensions through register clustering.
- Philip Brisk, Ajay K. Verma, Paolo Ienne:
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design.
- Peggy B. McGee, Steven M. Nowick:
An efficient algorithm for time separation of events in concurrent systems.
Resilient and regular circuits
3-D integration challenges
Applications of SAT and QBF
Physical synthesis comes of age
High quality test cases for verification
Advances in embedded systems
- Sushu Zhang, Karam S. Chatha:
Approximation algorithm for the temperature-aware scheduling problem.
- Jian-Jia Chen, Tei-Wei Kuo:
Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems.
- Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, Darrel Eric Johnson, Zheng Xu:
The FAST methodology for high-speed SoC/computer simulation.
- Marco D. Santambrogio, Seda Ogrenci Memik, Vincenzo Rana, Umut A. Acar, Donatella Sciuto:
A novel SoC design methodology combining adaptive software and reconfigurable hardware.
Can nano-photonic silicon circuits become an intra-chip interconnect technology?
- Eli Yablonovitch:
Can nano-photonic silicon circuits become an INTRA-chip interconnect technology?
Scaling formal verification
Advances in statistical timing analysis and optimization
Sequential synthesis and FPGA mapping
- Yu Hu, Victor Shih, Rupak Majumdar, Lei He:
Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping.
- Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert K. Brayton:
Combinational and sequential mapping with priority cuts.
- Dmitry Bufistov, Jordi Cortadella, Michael Kishinevsky, Sachin S. Sapatnekar:
A general model for performance optimization of sequential systems.
- Lei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig:
Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains.
Advances in routing and clock design
- Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang:
Skew aware polarity assignment in clock tree.
- Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Li, Yao-Wen Chang:
Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction.
- Fan Mo, Robert K. Brayton:
A simultaneous bus orientation and bused pin flipping algorithm.
- Hui Kong, Tan Yan, Martin D. F. Wong, Muhammet Mustafa Ozdal:
Optimal bus sequencing for escape routing in dense PCBs.
- Tan Yan, Martin D. F. Wong:
Untangling twisted nets for bus routing.
Improving delay test generation and performance predictors
- Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia:
Low-overhead design technique for calibration of maximum frequency at multiple operating points.
- Vikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah:
Variation-aware performance verification using at-speed structural test and statistical timing.
- Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo:
Estimation of delay test quality and its application to test generation.
- Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara:
Efficient path delay test generation based on stuck-at test generation using checker circuitry.
High level synthesis
Analog circuit optimization
- Xin Li, Brian Taylor, YuTsun Chien, Lawrence T. Pileggi:
Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization.
- Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Sensitivity analysis for oscillators.
- Guo Yu, Peng Li:
Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling.
- Jintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong Ken Yang:
Device-circuit co-optimization for mixed-mode circuit design via geometric programming.
- Cheng Zhuo, Huafeng Zhang, Rupak Samanta, Jiang Hu, Kangsheng Chen:
Modeling, optimization and control of rotary traveling-wave oscillator.
Test compression and test power
- Hao Fang, Chenguang Tong, Bo Yao, Xiaodi Song, Xu Cheng:
CacheCompress: a novel approach for test data compression with cache for IP embedded cores.
- Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei:
A hybrid scheme for compacting test responses with unknown values.
- Chia-Yi Lin, Hung-Ming Chen:
A selective pattern-compression scheme for power and test-data reduction.
- Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji:
Methodology for low power test pattern generation using activity threshold control logic.
Gate level physical synthesis
Interconnect modeling and optimization
Formal verification at higher levels of abstraction
- Qiang Ma, Evangeline F. Y. Young, K. P. Pun:
Analog placement with common centroid constraints.
- Chunta Chu, Xinyi Zhang, Lei He, Tong Jing:
Temperature aware microprocessor floorplanning considering application dependent power load.
- Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou:
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.
System-level synthesis and interconnect design
- Feng Wang, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan:
Variation-aware task allocation and scheduling for MPSoC.
- Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin:
A design flow dedicated to multi-mode architectures for DSP applications.
- Yi Wang, Dan Zhao:
The design and synthesis of a synchronous and distributed MAC protocol for wireless network-on-chip.
- Madhu Mutyam:
Selective shielding: a crosstalk-free bus encoding technique.
Advances in model order reduction techniques for interconnect analysis
Mosfet modeling for 45nm & beyond
Voltage assignment in floorplanning
Variation tolerant circuits
Advanced models for static timing analysis
- Chandramouli V. Kashyap, Chirayu S. Amin, Noel Menezes, Eli Chiprout:
A nonlinear cell macromodel for digital applications.
- Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail:
Including inductance in static timing analysis.
- Alexander V. Mitev, Dinesh Ganesan, Dheepan Shanmugasundaram, Yu Cao, Janet Meiling Wang:
A robust finite-point based gate model considering process variations.
- Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada:
Victim alignment in crosstalk aware timing analysis.
Variation aware timing verification
Reliability driven modeling and analysis for deep submicron technologies
Design automation and defect tolerance techniques for emerging technologies
- Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips.
- Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei Wang:
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture.
- M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli:
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays.
- Susmit Biswas, Gang Wang, Tzvetan S. Metodi, Ryan Kastner, Frederic T. Chong:
Combining static and dynamic defect-tolerance techniques for nanoscale memory systems.
Leakage power reduction
Power modeling and optimization
- Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He:
Efficient decoupling capacitance budgeting considering operation and process variations.
- Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs.
- Yuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao:
A novel technique for incremental analysis of on-chip power distribution networks.
- Xiaoyao Liang, Kerem Turgay, David Brooks:
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques.
Improving planarity and patterning
Model order reduction for parameterized and non-linear systems
Copyright © Mon Nov 2 20:41:33 2009
by Michael Ley (firstname.lastname@example.org)
- Bradley N. Bond, Luca Daniel:
Stabilizing schemes for piecewise-linear reduced order models via projection and weighting functions.
- Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng:
Parameterized model order reduction via a two-directional Arnoldi process.
- Wei Dong, Zhuo Feng, Peng Li:
Efficient VCO phase macromodel generation considering statistical parametric variations.
- Kin Cheong Sou, Alexandre Megretski, Luca Daniel:
Bounding L2 gain system error generated by approximations of the nonlinear vector field.
- Jaeha Kim, Kevin D. Jones, Mark A. Horowitz:
Variable domain transformation for linear PAC analysis of mixed-signal systems.