ICCAD 1999:
San Jose,
California,
USA
Jacob K. White, Ellen Sentovich (Eds.):
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999.
IEEE 1999, ISBN 0-7803-5832-5 BibTeX
- Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi:
Marsh: min-area retiming with setup and hold constraints.
2-6
Electronic Edition (link) BibTeX
- Robert M. Fuhrer, Steven M. Nowick:
OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic.
7-13
Electronic Edition (link) BibTeX
- Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.:
Bit-level arithmetic optimization for carry-save additions.
14-19
Electronic Edition (link) BibTeX
- Hussein Etawil, Shawki Areibi, Anthony Vannelli:
Attractor-repeller approach for global placement.
20-24
Electronic Edition (link) BibTeX
- Ingmar Neumann, Dominik Stoffel, Hendrik Hartje, Wolfgang Kunz:
Cell replication and redundancy elimination during placement for cycle time optimization.
25-30
Electronic Edition (link) BibTeX
- Jinan Lou, Wei Chen, Massoud Pedram:
Concurrent logic restructuring and placement for timing closure.
31-36
Electronic Edition (link) BibTeX
- Aiguo Xie, Peter A. Beerel:
Implicit enumeration of strongly connected components.
37-40
Electronic Edition (link) BibTeX
- In-Ho Moon, James H. Kukula, Thomas R. Shiple, Fabio Somenzi:
Least fixpoint approximations for reachability analysis.
41-44
Electronic Edition (link) BibTeX
- Hiroyuki Higuchi, Fabio Somenzi:
Lazy group sifting for efficient symbolic state traversal of FSMs.
45-49
Electronic Edition (link) BibTeX
- Wolfgang Günther, Rolf Drechsler:
Efficient manipulation algorithms for linearly transformed BDDs.
50-54
Electronic Edition (link) BibTeX
- Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli:
Noise analysis of non-autonomous radio frequency circuits.
55-60
Electronic Edition (link) BibTeX
- Mark M. Gourary, Sergey L. Ulyanov, Michael M. Zharov, Sergey G. Rusakov:
New methods for speeding up computation of Newton updates in harmonic balance.
61-64
Electronic Edition (link) BibTeX
- Maria del Mar Hershenson, Ali Hajimiri, Sunderarajan S. Mohan, Stephen P. Boyd, Thomas H. Lee:
Design and optimization of LC oscillators.
65-69
Electronic Edition (link) BibTeX
- Alper Demir, Peter Feldmann:
Modeling and simulation of the interference due to digital switching in mixed-signal ICs.
70-75
Electronic Edition (link) BibTeX
- Chunhong Chen, Majid Sarrafzadeh:
Provably good algorithm for low power consumption with dual supply voltages.
76-79
Electronic Edition (link) BibTeX
- Khurram Muhammad, Kaushik Roy:
A novel design methodology for high performance and low power digital filters.
80-83
Electronic Edition (link) BibTeX
- Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-Jong Chen, Xian-Jun Huang:
A bipartition-codec architecture to reduce power in pipelined circuits.
84-90
Electronic Edition (link) BibTeX
- Tatjana Serdar, Carl Sechen:
AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths.
91-97
Electronic Edition (link) BibTeX
- Serkan Askar, Maciej J. Ciesielski:
Analytical approach to custom datapath design.
98-101
Electronic Edition (link) BibTeX
- Yanbin Jiang, Sachin S. Sapatnekar:
An integrated algorithm for combined placement and libraryless technology mapping.
102-106
Electronic Edition (link) BibTeX
- Min Zhao, Sachin S. Sapatnekar:
Timing-driven partitioning for two-phase domino and mixed static/domino implementations.
107-110
Electronic Edition (link) BibTeX
- Ki-Wook Kim, C. L. Liu, Sung-Mo Kang:
Implication graph based domino logic synthesis.
111-114
Electronic Edition (link) BibTeX
- Shih-Chieh Chang, Jung-Cheng Chuang, Zhong-Zhen Wu:
Synthesis for multiple input wires replacement of a gate for wiring consideration.
115-119
Electronic Edition (link) BibTeX
- Tuyen V. Nguyen, Peter O'Brien, David W. Winston:
Transient sensitivity computation for transistor level analysis and tuning.
120-123
Electronic Edition (link) BibTeX
- Yi-Kan Cheng, Sung-Mo Kang:
An efficient method for hot-spot identification in ULSI circuits.
124-127
Electronic Edition (link) BibTeX
- Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez:
A scalable substrate noise coupling model for mixed-signal ICs.
128-131
Electronic Edition (link) BibTeX
- Pinhong Chen, Kurt Keutzer:
Towards true crosstalk noise analysis.
132-138
Electronic Edition (link) BibTeX
- Paul Tafertshofer, Andreas Ganz:
SAT based ATPG using fast justification and propagation in the implication graph.
139-146
Electronic Edition (link) BibTeX
- Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
Techniques for improving the efficiency of sequential circuit test generation.
147-151
Electronic Edition (link) BibTeX
- Fatih Kocan, Daniel G. Saab:
Concurrent D-algorithm on reconfigurable hardware.
152-156
Electronic Edition (link) BibTeX
- Ion I. Mandoiu, Vijay V. Vazirani, Joseph L. Ganley:
A new heuristic for rectilinear Steiner trees.
157-162
Electronic Edition (link) BibTeX
- Jason Cong, Jie Fang, Kei-Yong Khoo:
An implicit connection graph maze routing algorithm for ECO routing.
163-167
Electronic Edition (link) BibTeX
- Yu Chen, Andrew B. Kahng, Gang Qu, Alexander Zelikovsky:
The associative-skew clock routing problem.
168-172
Electronic Edition (link) BibTeX
- Shantanu Dutt, Vimalvel Shanmugavel, Steven Trimberger:
Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays.
173-177
Electronic Edition (link) BibTeX
- David S. Kung, Ruchir Puri:
Optimal P/N width ratio selection for standard cell libraries.
178-184
Electronic Edition (link) BibTeX
- Rajeev Murgai:
Performance optimization under rise and fall parameters.
185-190
Electronic Edition (link) BibTeX
- Yutaka Tamiya:
Performance optimization using separator sets.
191-194
Electronic Edition (link) BibTeX
- Martin Charles Golumbic, Aviad Mintz:
Factoring logic functions using graph partitioning.
195-199
Electronic Edition (link) BibTeX
- Bernard N. Sheehan:
TICER: realizable reduction of extracted RC circuits.
200-203
Electronic Edition (link) BibTeX
- Anirudh Devgan, Peter R. O'Brien:
Realizable reduction for RC interconnect circuits.
204-207
Electronic Edition (link) BibTeX
- Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng:
RLC interconnect delay estimation via moments of amplitude and phase response.
208-213
Electronic Edition (link) BibTeX
- Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi:
Practical considerations for passive reduction of RLC circuits.
214-220
Electronic Edition (link) BibTeX
- Ellen Sentovich, David L. Dill, Serdar Tasiran:
Formal verification meets simulation (tutorial abstract).
221
Electronic Edition (link) BibTeX
- Mattan Kamon, Steve McCormick, Ken Sheperd:
Interconnect parasitic extraction in the digital IC design methodology.
223-231
Electronic Edition (link) BibTeX
- Christoph Albrecht, Bernhard Korte, Jürgen Schietke, Jens Vygen:
Cycle time and slack optimization for VLSI-chips.
232-238
Electronic Edition (link) BibTeX
- Ivan S. Kourtev, Eby G. Friedman:
Clock skew scheduling for improved reliability via quadratic programming.
239-243
Electronic Edition (link) BibTeX
- Chandramouli Visweswariah, Andrew R. Conn:
Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation.
244-252
Electronic Edition (link) BibTeX
- Rainer Leupers, Peter Marwedel:
Function inlining under code size constraints for embedded processors.
253-256
Electronic Edition (link) BibTeX
- Daniel Benyamin, William H. Mangione-Smith:
Function unit specialization through code analysis.
257-260
Electronic Edition (link) BibTeX
- Margarida F. Jacome, Gustavo de Veciana:
Lower bound on latency for VLIW ASIP datapaths.
261-269
Electronic Edition (link) BibTeX
- Tony Givargis, Jörg Henkel, Frank Vahid:
Interface and cache power exploration for core-based embedded system design.
270-273
Electronic Edition (link) BibTeX
- Eui-Young Chung, Luca Benini, Giovanni De Micheli:
Dynamic power management using adaptive learning tree.
274-279
Electronic Edition (link) BibTeX
- Giuseppe Bernacchia, Marios C. Papaefthymiou:
Analytical macromodeling for high-level power estimation.
280-283
Electronic Edition (link) BibTeX
- Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino:
Parameterized RTL power models for combinational soft macros.
284-288
Electronic Edition (link) BibTeX
- Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer:
Validation and test generation for oscillatory noise in VLSI interconnects.
289-296
Electronic Edition (link) BibTeX
- Michael Cuviello, Sujit Dey, Xiaoliang Bai, Yi Zhao:
Fault modeling and simulation for crosstalk in system-on-chip interconnects.
297-303
Electronic Edition (link) BibTeX
- Alfred V. Gomes, Abhijit Chatterjee:
Robust optimization based backtrace method for analog circuits.
304-308
Electronic Edition (link) BibTeX
- Luca P. Carloni, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli:
A methodology for correct-by-construction latency insensitive design.
309-315
Electronic Edition (link) BibTeX
- Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev:
What is the cost of delay insensitivity?
316-323
Electronic Edition (link) BibTeX
- Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens:
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions.
324-331
Electronic Edition (link) BibTeX
- Sung Tae Jung, Chris J. Myers:
Direct synthesis of timed asynchronous circuits.
332-338
Electronic Edition (link) BibTeX
- David L. Rhodes, Wayne Wolf:
Co-synthesis of heterogeneous multiprocessor systems using arbitrated communication.
339-342
Electronic Edition (link) BibTeX
- Gang Qu, Miodrag Potkonjak:
Power minimization using system-level partitioning of applications with quality of service requirements.
343-346
Electronic Edition (link) BibTeX
- Felice Balarin:
Worst-case analysis of discrete systems.
347-353
Electronic Edition (link) BibTeX
- Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani:
Integrated floorplanning and interconnect planning.
354-357
Electronic Edition (link) BibTeX
- Jason Cong, Tianming Kong, David Zhigang Pan:
Buffer block planning for interconnect-driven floorplanning.
358-363
Electronic Edition (link) BibTeX
- Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang:
A clustering- and probability-based approach for time-multiplexed FPGA partitioning.
364-369
Electronic Edition (link) BibTeX
- Janet Meiling Wang, Ernest S. Kuh, Qingjian Yu:
The Chebyshev expansion based passive model for distributed interconnect networks.
370-375
Electronic Edition (link) BibTeX
- Emad Gad, Michel S. Nakhla:
Model reduction for DC solution of large nonlinear circuits.
376-379
Electronic Edition (link) BibTeX
- Jing-Rebecca Li, Jacob White:
Efficient model reduction of interconnect via approximate system gramians.
380-384
Electronic Edition (link) BibTeX
- Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
A framework for testing core-based systems-on-a-chip.
385-390
Electronic Edition (link) BibTeX
- Krishnendu Chakrabarty:
Test scheduling for core-based systems.
391-394
Electronic Edition (link) BibTeX
- Qiushuang Zhang, Ian G. Harris:
Partial BIST insertion to eliminate data correlation.
395-399
Electronic Edition (link) BibTeX
- Huiqun Liu, D. F. Wong:
A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning.
400-405
Electronic Edition (link) BibTeX
- Inki Hong, Miodrag Potkonjak, Lisa Guerra:
Throughput optimization of general non-linear computations.
406-409
Electronic Edition (link) BibTeX
- Junhyung Um, Taewhan Kim, C. L. Liu:
Optimal allocation of carry-save-adders in arithmetic optimization.
410-413
Electronic Edition (link) BibTeX
- Soha Hassoun, Carolyn McCreary:
Regularity extraction via clan-based structural circuit decomposition.
414-419
Electronic Edition (link) BibTeX
- Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Repeater insertion in tree structured inductive interconnect.
420-424
Electronic Edition (link) BibTeX
- Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz:
Interconnect scaling implications for CAD.
425-429
Electronic Edition (link) BibTeX
- Charles J. Alpert, Anirudh Devgan, Stephen T. Quay:
Is wire tapering worthwhile?
430-436
Electronic Edition (link) BibTeX
- Michael W. Beattie, Lawrence T. Pileggi:
Electromagnetic parasitic extraction via a multipole method with hierarchical refinement.
437-444
Electronic Edition (link) BibTeX
- A. J. Dammers, N. P. van der Meijs:
Virtual screening: a step towards a sparse partial inductance matrix.
445-452
Electronic Edition (link) BibTeX
- Junfeng Wang, Johannes Tausch, Jacob K. White:
A wide frequency range surface integral formulation for 3-D RLC extraction.
453-458
Electronic Edition (link) BibTeX
- Sani R. Nassif, Tuyen V. Nguyen:
SOI technology and tools (abstract).
459
Electronic Edition (link) BibTeX
- Rolf Ernst, Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar:
System level design and debug of high-performance embedded media systems (tutorial).
461
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
An approach for improving the levels of compaction achieved by vector omission.
463-466
Electronic Edition (link) BibTeX
- Bapiraju Vinnakota:
Deep submicron defect detection with the energy consumption ratio.
467-470
Electronic Edition (link) BibTeX
- Pankaj Pant, Abhijit Chatterjee:
Efficient diagnosis of path delay faults in digital logic circuits.
471-476
Electronic Edition (link) BibTeX
- Preeti Ranjan Panda:
Memory bank customization and assignment in behavioral synthesis.
477-481
Electronic Edition (link) BibTeX
- Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha:
Memory binding for performance optimization of control-flow intensive behaviors.
482-488
Electronic Edition (link) BibTeX
- Dirk Herrmann, Rolf Ernst:
Improved interconnect sharing by identity operation insertion.
489-493
Electronic Edition (link) BibTeX
- Thomas A. Henzinger, Xiaojun Liu, Shaz Qadeer, Sriram K. Rajamani:
Formal specification and verification of a dataflow processor array.
494-499
Electronic Edition (link) BibTeX
- Dragos Lungeanu, C.-J. Richard Shi:
Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization.
500-504
Electronic Edition (link) BibTeX
- Harry Hsieh, Felice Balarin:
Synchronous equivalence for embedded systems: a tool for design exploration.
505-510
Electronic Edition (link) BibTeX
- Rajeev Murgai:
On the global fanout optimization problem.
511-515
Electronic Edition (link) BibTeX
- Peyman Rezvani, Amir H. Ajami, Massoud Pedram, Hamid Savoj:
LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay.
516-519
Electronic Edition (link) BibTeX
- Jie-Hong Roland Jiang, Iris Hui-Ru Jiang:
Optimum loading dispersion for high-speed tree-type decision circuitry.
520-525
Electronic Edition (link) BibTeX
- Clayton B. McDonald, Randal E. Bryant:
Symbolic functional and timing verification of transistor-level circuits.
526-530
Electronic Edition (link) BibTeX
- Kenneth L. Shepard, Dae-Jin Kim:
Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis.
531-538
Electronic Edition (link) BibTeX
- Alexander Saldanha:
Functional timing optimization.
539-543
Electronic Edition (link) BibTeX
- Yuji Kukimoto, Robert K. Brayton:
Timing-safe false path removal for combinational modules.
544-550
Electronic Edition (link) BibTeX
- Rachid Helaihel, Kunle Olukotun:
JMTP: an architecture for exploiting concurrency in embedded Java applications with real-time considerations.
551-557
Electronic Edition (link) BibTeX
- Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich:
FunState - an internal design representation for codesign.
558-565
Electronic Edition (link) BibTeX
- Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Fast performance analysis of bus-based system-on-chip communication architectures.
566-573
Electronic Edition (link) BibTeX
- Andreas Kuehlmann, Kenneth L. McMillan, Robert K. Brayton:
Probabilistic state space search.
574-579
Electronic Edition (link) BibTeX
- Jules P. Bergmann, Mark Horowitz:
Improving coverage analysis and test generation for large designs.
580-583
Electronic Edition (link) BibTeX
- Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz:
Modeling design constraints and biasing in simulation using BDDs.
584-590
Electronic Edition (link) BibTeX
- Edoardo Charbon, Ilhami Torunoglu:
Copyright protection of designs based on multi source IPs.
591-595
Electronic Edition (link) BibTeX
- Darko Kirovski, Miodrag Potkonjak:
Localized watermarking: methodology and application to operation scheduling.
596-599
Electronic Edition (link) BibTeX
- Andrew B. Kahng, Darko Kirovski, Stefanus Mantik, Miodrag Potkonjak, Jennifer L. Wong:
Copy detection for intellectual property protection of VLSI designs.
600-605
Electronic Edition (link) BibTeX
- Jacob White, Gary K. Fedder, Tamal Mukherjee:
Path toward future CAD environments for MEMS (tutorial abstract).
606
Electronic Edition (link) BibTeX
- Nikil D. Dutt, Eric Foster:
Design of a set-top box system on a chip (abstract).
608
Electronic Edition (link) BibTeX
- Nikil D. Dutt, Brian Kelley:
On the rapid prototyping and design of a wireless communication system on a chip (abstract).
609
Electronic Edition (link) BibTeX
- Jacob White, Jacob Avidan, Abe Elfadel, D. F. Wong:
Advances in transistor timing, simulation, and optimization (tutorial abstract).
611
Electronic Edition (link) BibTeX
- Reinaldo A. Bergamaschi, Brian M. Barry, John Duimovich:
Embedded Java: techniques and applications (tutorial abstract).
613
Electronic Edition (link) BibTeX
Copyright © Wed Jun 4 18:38:42 2008
by Michael Ley (ley@uni-trier.de)
