ICCAD 1995: San Jose, California, USA

• Robert B. Jones, David L. Dill, Jerry R. Burch:
  Efficient validity checking for processor verification. 2-6
  
• Mark Aagaard, Carl-Johan H. Seger:
  The formal verification of a pipelined double-precision IEEE floating-point multiplier. 7-10
  
• K. J. Singh, P. A. Subrahmanyam:
  Extracting RTL models from transistor netlists. 11-17
  
• Taku Uchino, Fumihiro Minami, Takashi Mitsuhashi, Nobuyuki Goto:
  Switching activity analysis using Boolean approximation method. 20-25
  
• Peter A. Beerel, Kenneth Y. Yun, Steven M. Nowick, Pei-Chuan Yeh:
  Estimation and bounding of energy consumption in burst-mode control circuits. 26-33
  
• Tan-Li Chou, Kaushik Roy:
  Statistical estimation of sequential circuit activity. 34-37
  
• Mike Chou, Jacob K. White:
  Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect. 40-44
  
• Byron Krauter, Lawrence T. Pileggi:
  Generating sparse partial inductance matrices with guaranteed stability. 45-52
  
• Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang:
  Addressing high frequency effects in VLSI interconnects with full wave model and CFH. 53-56
  
• Shantanu Ganguly, Shervin Hojat:
  Clock distribution design and verification for PowerPC microprocessors. 58-61
  
• Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh:
  Activity-driven clock design for low power circuits. 62-65
  
• Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao:
  Bounded-skew clock and Steiner routing under Elmore delay. 66-71
  
• Shipra Panda, Fabio Somenzi:
  Who are the variables in your neighborhood. 74-77
  
• Kiyoharu Hamaguchi, Akihito Morita, Shuzo Yajima:
  Efficient construction of binary moment diagrams for verifying arithmetic circuits. 78-82
  
• Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok:
  Be careful with don't cares. 83-86
  
• Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich:
  Pattern generation for a deterministic BIST scheme. 88-94
  
• Albrecht P. Stroele, Hans-Joachim Wunderlich:
  Test register insertion with minimum hardware cost. 95-101
  
• Chen-Yang Pan, Kwang-Ting Cheng:
  Pseudo-random testing and signature analysis for mixed-signal circuits. 102-107
  
• Anirudh Devgan:
  Efficient and accurate transient simulation in charge-voltage plane. 110-114
  
• D. Zhou, N. Chen, W. Cai:
  A fast wavelet collocation method for high-speed VLSI circuit simulation. 115-122
  
• Lars Hedrich, Erich Barke:
  A formal approach to nonlinear analog circuit verification. 123-127
  
• Rohini Gupta, Lawrence T. Pileggi:
  Constrained multivariable optimization of transmission lines with general topologies. 130-137
  
• John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin:
  Optimal wire sizing and buffer insertion for low power and a generalized delay model. 138-143
  
• Noel Menezes, Ross Baldick, Lawrence T. Pileggi:
  A sequential quadratic programming approach to concurrent gate and wire sizing. 144-151
  
• Kavita Ravi, Fabio Somenzi:
  High-density reachability analysis. 154-158
  
• Edmund M. Clarke, Masahiro Fujita, Xudong Zhao:
  Hybrid decision diagrams. 159-163
  
• Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev:
  Synthesizing Petri nets from state-based models. 164-171
  
• Hussain Al-Asaad, John P. Hayes:
  Design verification via simulation and automatic test pattern generation. 174-180
  
• Yiming Gong, Sreejit Chakravarty:
  On adaptive diagnostic test generation. 181-184
  
• Brian Chess, David B. Lavo, F. Joel Ferguson, Tracy Larrabee:
  Diagnosis of realistic bridging faults with single stuck-at information. 185-192
  
• Nishath K. Verghese, David J. Allstot:
  SUBTRACT: a program for the efficient evaluation of substrate parasitics in integrated circuits. 194-198
  
• T. Smedes, N. P. van der Meijs, Arjan J. van Genderen:
  Extraction of circuit models for substrate cross-talk. 199-206
  
• Kevin J. Kerns, Ivan L. Wemple, Andrew T. Yang:
  Stable and efficient reduction of substrate model networks using congruence transforms. 207-214
  
• Hannah Honghua Yang, D. F. Wong:
  New algorithms for min-cut replication in partitioned circuits. 216-222
  
• Jianmin Li, John Lillis, Chung-Kuan Cheng:
  Linear decomposition algorithm for VLSI design applications. 223-228
  
• Lung-Tien Liu, Ming-Ter Kuo, Shih-Chen Huang, Chung-Kuan Cheng:
  A gradient method on the initial partition of Fiduccia-Mattheyses algorithm. 229-234
  
• Randal E. Bryant:
  Binary decision diagrams and beyond: enabling technologies for formal verification. 236-243
  
• Lawrence T. Pileggi:
  Coping with RC(L) interconnect design headaches. 246-253
  
• Michel R. C. M. Berkelaar, Lukas P. P. P. van Ginneken:
  Efficient orthonormality testing for synthesis with pass-transistor selectors. 256-263
  
• Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness:
  Logic decomposition during technology mapping. 264-271
  
• Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, Shiv Prakash:
  Efficient use of large don't cares in high-level and logic synthesis. 272-278
  
• Pai H. Chou, Ross B. Ortega, Gaetano Borriello:
  Interface co-synthesis techniques for embedded systems. 280-287
  
• Ti-Yen Yen, Wayne Wolf:
  Communication synthesis for distributed embedded systems. 288-294
  
• Miodrag Potkonjak, Sujit Dey, Kazutoshi Wakabayashi:
  Design-for-debugging of application specific designs. 295-301
  
• Manfred Henftling, Hannes C. Wittmann, Kurt Antreich:
  A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization. 304-309
  
• Anand Raghunathan, Srimat T. Chakradhar:
  Acceleration techniques for dynamic vector compaction. 310-317
  
• Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz:
  LOT: logic optimization with testability-new transformations using recursive learning. 318-325
  
• Tanay Karnik, Sung-Mo Kang:
  An empirical model for accurate estimation of routing delay in FPGAs. 328-331
  
• Sudip K. Nag, Rob A. Rutenbar:
  Performance-driven simultaneous place and route for island-style FPGAs. 332-338
  
• Wai-Kei Mak, D. F. Wong:
  Board-level multi-terminal net routing for FPGA-based logic emulation. 339-344
  
• Amit Chowdhary, John P. Hayes:
  Technology mapping for field-programmable gate arrays using integer programming. 346-352
  
• Hiroshi Sawada, Takayuki Suyama, Akira Nagoya:
  Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization. 353-358
  
• Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
  Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. 359-363
  
• Chin-Chi Teng, Anthony M. Hill, Sung-Mo Kang:
  Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits. 366-370
  
• Hakan Yalcin, John P. Hayes:
  Hierarchical timing analysis using conditional delays. 371-377
  
• Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe:
  Performance estimation of embedded software with instruction cache modeling. 380-387
  
• Ashok Sudarsanam, Sharad Malik:
  Memory bank and register allocation in software synthesis for ASIPs. 388-392
  
• Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang:
  Instruction selection using binate covering for code size optimization. 393-399
  
• Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia:
  Fast discrete function evaluation using decision diagrams. 402-407
  
• Pranav Ashar, Sharad Malik:
  Fast functional simulation using branching programs. 408-412
  
• Scott Woods, Giorgio Casinovi:
  Gate-level simulation of digital circuits using multi-valued Boolean algebras. 413-419
  
• Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru:
  An iterative gate sizing approach with accurate delay evaluation. 422-427
  
• R. Iris Bahar, Fabio Somenzi:
  Boolean techniques for low power driven re-synthesis. 428-432
  
• Sasan Iman, Massoud Pedram:
  Two-level logic minimization for low power. 433-438
  
• Wing Hang Wong, Rajiv Jain:
  PARAS: system-level concurrent partitioning and scheduling. 440-445
  
• Miodrag Potkonjak, Wayne Wolf:
  Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques. 446-451
  
• Amir H. Farrahi, Majid Sarrafzadeh:
  System partitioning to maximize sleep time. 452-455
  
• Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinatori Watanabe:
  A delay model for logic synthesis of continuously-sized networks. 458-462
  
• Sachin S. Sapatnekar, Weitong Chuang:
  Power vs. delay in gate sizing: conflicting objectives? 463-466
  
• Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn:
  Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. 467-470
  
• Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani:
  Rectangle-packing-based module placement. 472-479
  
• Weiping Shi:
  An optimal algorithm for area minimization of slicing floorplans. 480-484
  
• Anmol Mathur, K. C. Chen, C. L. Liu:
  Re-engineering of timing constrained placements for regular architectures. 485-490
  
• Farid N. Najm:
  Power estimation techniques for integrated circuits. 492-499
  
• Paul E. R. Lippens, Vijay Nagasamy, Wayne Wolf:
  CAD challenges in multimedia computing. 502-508
  
• Herman Schmit, Donald E. Thomas:
  Address generation for memories containing multiple arrays. 510-514
  
• Gjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wuytack, Francky Catthoor:
  Background memory management for dynamic data structure intensive processing systems. 515-520
  
• Wei Zhao, Christos A. Papachristou:
  Architectural partitioning of control memory for application specific programmable processors. 521-526
  
• Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen:
  Cost-free scan: a low-overhead scan path design methodology. 528-533
  
• Sujit Dey, Vijay Gangaram, Miodrag Potkonjak:
  A controller-based design-for-testability technique for controller-data path circuits. 534-540
  
• Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
  On testable multipliers for fixed-width data path architectures. 541-547
  
• Jan Crols, Stéphane Donnay, Michiel Steyaert, Georges G. E. Gielen:
  A high-level design and optimization tool for analog RF receiver front-ends. 550-553
  
• S. R. Kadivar, Doris Schmitt-Landsiedel, H. Klar:
  A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters. 554-561
  
• Eduardo J. Peralías, Adoración Rueda, José Luis Huertas:
  Statistical behavioral modeling and characterization of A/D converters. 562-566
  
• Jason Cong, Lei He:
  Optimal wiresizing for interconnects with multiple sources. 568-574
  
• Tianxiong Xue, Ernest S. Kuh:
  Post routing performance optimization via multi-link insertion and non-uniform wiresizing. 575-580
  
• Man-Fai Yu, Wayne Wei-Ming Dai:
  Single-layer fanout routing and routability analysis for Ball Grid Arrays. 581-586
  
• Nelson L. Passos, Edwin Hsing-Mean Sha:
  Push-up scheduling: Optimal polynomial-time resource constrained scheduling for multi-dimensional applications. 588-591
  
• Fermín Sánchez:
  Time-Constrained Loop Pipelining. 592
  
• Anand Raghunathan, Niraj K. Jha:
  An iterative improvement algorithm for low power data path synthesis. 597-602
  
• Robert M. Fuhrer, Bill Lin, Steven M. Nowick:
  Symbolic hazard-free minimization and encoding of asynchronous finite state machines. 604-611
  
• Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Sequential synthesis using S1S. 612-617
  
• Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich:
  Design based analog testing by Characteristic Observation Inference. 620-626
  
• Giri Devarayanadurg, Mani Soma:
  Dynamic test signal design for analog ICs. 627-630
  
• Chauchin Su, Shenshung Chiang, Shyh-Jye Jou:
  Impulse response fault model and fault extraction for functional level analog circuit diagnosis. 631-636
  
• Hirendu Vaishnav, Massoud Pedram:
  Delay optimal partitioning targeting low power VLSI circuits. 638-643
  
• Roman Kuznar, Franc Brglez:
  PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists. 644-649
  
• David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska:
  Circuit partitioning with logic perturbation. 650-655
  
• Balakrishnan Iyer, Ramesh Karri, Israel Koren:
  Phantom redundancy: a high-level synthesis approach for manufacturability. 658-661
  
• Elof Frank, Thomas Lengauer:
  APPlaUSE: Area and performance optimization in a unified placement and synthesis environment. 662-667
  
• Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
  Synthesis of multiplier-less FIR filters with minimum number of additions. 668-671
  
• Peter Dahlgren:
  A multiple-dominance switch-level model for simulation of short faults. 674-680
  
• Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai:
  Fault emulation: a new approach to fault grading. 681-686
  
• Irith Pomeranz, Sudhakar M. Reddy:
  Functional test generation for delay faults in combinational circuits. 687-694
  
• Kannan Krishna, Stephen W. Director:
  A novel methodology for statistical parameter extraction. 696-699
  
• Boris Troyanovsky, Zhiping Yu, Lydia So, Robert W. Dutton:
  Relaxation-based harmonic balance technique for semiconductor device simulation. 700-703
  
• Haifang Liao, Wayne Wei-Ming Dai:
  Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels. 704-709
  
• Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
  A unified approach to topology generation and area optimization of general floorplans. 712-715
  
• Jaewon Kim, Sung-Mo Kang:
  A timing-driven data path layout synthesis with integer programming. 716-719
  
• Kai-Yuan Chao, D. F. Wong:
  Signal integrity optimization on the pad assignment for high-speed VLSI design. 720-725
  
• Huey-Yih Wang, Robert K. Brayton:
  Multi-level logic optimization of FSM networks. 728-735
  
• Krishna P. Belkhale, Alexander J. Suess:
  Timing analysis with known false sub graphs. 736-740