HiPEAC 2005: Barcelona, Spain

Invited Program

• Markus Levy:
  Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications. 3-4
  
• Per Stenström:
  The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges. 5
  
• Hyunseok Lee, Yuan Lin, Yoav Harel, Mark Woh, Scott A. Mahlke, Trevor N. Mudge, Krisztián Flautner:
  Software Defined Radio - A High Performance Embedded Challenge. 6-26
  

Analysis and Evaluation Techniques

• Grigori Fursin, Albert Cohen, Michael F. P. O'Boyle, Olivier Temam:
  A Practical Method for Quickly Evaluating Program Optimizations. 29-46
  
• Michael Van Biesbrouck, Lieven Eeckhout, Brad Calder:
  Efficient Sampling Startup for Sampled Processor Simulation. 47-67
  
• Jia Yu, Jun Yang, Shaojie Chen, Yan Luo, Laxmi N. Bhuyan:
  Enhancing Network Processor Simulation Speed with Statistical Input Sampling. 68-83
  

Novel Memory and Interconnect Architectures

• Ke Ning, David R. Kaeli:
  Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems. 87-101
  
• Michael J. Geiger, Sally A. McKee, Gary S. Tyson:
  Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation. 102-115
  
• David Moloney, Dermot Geraghty, Colm McSweeney, Ciarán McElroy:
  Streaming Sparse Matrix Compression/Decompression. 116-129
  
• Gansha Wu, Xin Zhou, Guei-Yuan Lueh, Jesse Z. Fang, Peng Guo, Jinzhan Peng, Victor Ying:
  XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs. 130-149
  

Security Architecture

• Weidong Shi, Chenghuai Lu, Hsien-Hsin S. Lee:
  Memory-Centric Security Architecture. 153-168
  
• Abdulhadi Shoufan, Sorin A. Huss, Murtuza Cutleriwala:
  A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management. 169-183
  
• Mahadevan Gomathisankaran, Akhilesh Tyagi:
  Arc3D: A 3D Obfuscation Architecture. 184-199
  

Novel Compiler and Runtime Techniques

• Jinpyo Kim, Sreekumar V. Kodakara, Wei-Chung Hsu, David J. Lilja, Pen-Chung Yew:
  Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations. 203-217
  
• Sebastian Pop, Albert Cohen, Georges-André Silber:
  Induction Variable Analysis with Delayed Abstractions. 218-232
  
• Dries Buytaert, Kris Venstermans, Lieven Eeckhout, Koen De Bosschere:
  Garbage Collection Hints. 233-248
  

Domain Specific Architectures

• Bengu Li, Ganesh Venkatesh, Brad Calder, Rajiv Gupta:
  Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors. 251-265
  
• Pedro Javier García, Jose Flich, José Duato, Ian Johnson, Francisco J. Quiles, Finbar Naven:
  Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture. 266-285
  
• Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustin Fernández, Roger Espasa:
  A Single (Unified) Shader GPU Microarchitecture for Embedded Systems. 286-301
  
• Hyun-Gyu Kim, Hyeong-Cheol Oh:
  A Low-Power DSP-Enhanced 32-Bit EISC Processor. 302-316