15. FPL 2005:
Tampere,
Finland
Tero Rissa, Steven J. E. Wilton, Philip Heng Wai Leong (Eds.):
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005.
IEEE 2005, ISBN 0-7803-9362-7 
Embedded Soft Processors
Logic Synthesis
Networking Applications 1
Chip Communication Architectures
CAD for Coarse-Grained Logic
SAT Solvers and Neural Networks
Chip Architectures
Arithmetic
Video Processing Applications 1
Run-Time Reconfigurable Architectures and Applications
Routing Characterization
Multidimensional Processing
Network on Chip Architectures
Tools and Methods for Run-Time Reconfiguration
Implementation Techniques
Defect Tolerance
Compilation Methods 1
Cryptography Applications
Asynchronous Architectures
Compilation Methods 2
Bio-Inspired Computing
- Iosifina Pournara, Christos-Savvas Bouganis, George A. Constantinides:
FPGA-Accelerated Reconstruction of Gene Regulatory Networks.
323-328
- Peter Zipf, Oliver Soffke, Andre Schumacher, Radu Dogaru, Manfred Glesner:
Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata.
329-334
- Peter Zipf, Oliver Soffke, Andre Schumacher, Clemens Schlachta, Radu Dogaru, Manfred Glesner:
A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata.
335-340
System Architecture Exploration and Evaluation
Communication Synthesis and High Level Design
MPEG Applications
- Olli Lehtoranta, Erno Salminen, Ari Kulmala, Marko Hännikäinen, Timo D. Hämäläinen:
A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC.
380-385
- Michael Janiaut, Camel Tanougast, Hassan Rabah, Yves Berviller, Christian Mannino, Serge Weber:
Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis.
386-390
- Kristof Denolf, Adrian Chirila-Rus, Robert D. Turney, Paul R. Schumacher, Kees A. Vissers:
Memory Efficient Design of an MPEG-4 Video Encoder for FPGAs.
391-396
Fault Tolerant Architectures and Systems
Placement
Security Attacks and Detection
Video Processing Architectures and Systems
Emulation and Simulation
Networking Applications 2
Poster Session 1
- Rawat Siripokarpirom:
A Run-Time Reconfigurable Hardware Infrastructure for IP-Core Evaluation and Test.
505-508
- Sinan Yalcin, Hasan F. Ates, Ilker Hamzaoglu:
A High Performance Hardware Architecture for an SAD Reuse based Hierarchical Motion Estimation Algorithm for H.264 Video Coding.
509-514
- Elias Todorovich, F. Angarita, Javier Valls, Eduardo I. Boemo:
Statistical Power Estimation for FPGA.
515-518
- Georg Acher, Rainer Buchty, Carsten Trinitis:
CPU-independent Assembler in an FPGA.
519-522
- Carlos Leong, P. Bento, Pedro Rodrigues, Andreia Trindade, J. C. Silva, Pedro Lousã, Joel Rego, J. Nobre, João Varela, João Paulo Teixeira, Isabel C. Teixeira:
Design and Test Methodology for a Reconfigurable PEM Data Acquisition Electronics System.
523-526
- Ronald Hecht, Stephan Kubisch, Andreas Herrholtz, Dirk Timmermann:
Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs.
527-530
- Antonio García, Javier Ramírez, Uwe Meyer-Bäse, Encarnación Castillo, Antonio Lloris-Ruíz:
Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks.
531-534
- F. Angarita, A. Perez-Pascual, T. Sansaloni, Javier Valls:
Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates.
535-538
- David Narh Amanor, Viktor Bunimov, Christof Paar, Jan Pelzl, Manfred Schimmler:
Efficient Hardware Architectures for Modular Multiplication on FPGAs.
539-542
- Jawad Khan, Ranga Vemuri:
Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing Nodes.
543-546
- José-Javier Martínez, F. Javier Toledo, F. Javier Garrigós, José Manuel Ferrández de Vicente:
FPGA Implementation of an Area-Time Efficient FIR Filter Core Using a Self-Clocked Approach.
547-550
- Artur Schiefer, Udo Kebschull:
Optimization of Start-Up Time and Quiescent Power Consumption of FPGAs.
551-554
- Yonghong Xu, Mohammed A. S. Khalid:
QPF: Efficient Quadratic Placement for FPGAs.
555-558
- Jacobo Alvarez, Jorge Marcos, Santiago Fernandez:
Safe PLD-based Programmable Controllers.
559-562
- Juanjo Noguera, Rosa M. Badia:
Performance and Energy Analysis of Task-Level Graph Transformation Techniques for Dynamically Reconfigurable Architectures.
563-567
Poster Session 2
- Klaus Danne, Marco Platzner:
A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware.
568-573
- Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano:
A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGA.
574-577
- Francisco Cardells-Tormo, Pep-Lluis Molinet, Jordi Sempere-Agulló, Luis Baldez, Marc Bautista-Palacios:
Area-Efficient 2-D Shift-Variant Convolvers for FPGA-based Digital Image Processing.
578-581
- Martin J. Pearson, Chris Melhuish, Anthony G. Pipe, Mokhtar Nibouche, Ian Gilhespy, Kevin N. Gurney, Benjamin Mitchinson:
Design and FPGA Implementation of an Embedded Real-Time Biologically Plausible Spiking Neural Network Processor.
582-585
- Hendrik Lange, Hartmut Schröder:
Evaluation Strategies for Coarse Grained Reconfigurable Architectures.
586-589
- Kelly Nasi, Martin Danek, Theodoros Karoubalis, Zdenek Pohl:
Figaro - An Automatic Tool Flow for Designs with Dynamic Reconfiguration.
590-593
- Maurice Keller, Tim Kerins, William P. Marnane:
FPGA Implementation of a GF(24M) Multiplier for use in Pairing Based Cryptosystems.
594-597
- Xavier Revés, Vuk Marojevic, Ramon Ferrús, Antoni Gelonch:
FPGA's Middleware for Software Defined Radio Applications.
598-601
- Dragomir Milojevic:
Implementation of Ranking Filters on General Purpose and Reconfigurable Architecture Based on High Density FPGA Devices.
602-605
- Tapani Ahonen, Jari Nurmi:
Integration of a NoC-Based Multimedia Processing Platform.
606-611
- Tom Van Court, Martin C. Herbordt:
LAMP: A Tool Suite for Families of FPGA-Based Application Accelerators.
612-617
- Sajid Baloch, Imran Ahmed, Tughrul Arslan, Adrian Stoica:
Low Power Domain-Specific Reconfigurable Array for Discrete Wavelet Transforms Targeting Multimedia Applications.
618-621
- Bingfeng Mei, Francisco-Javier Veredas, Bart Masschelein:
Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture.
622-625
- Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides:
Parameterized Logic Power Consumption Models for FPGA based Systems.
626-629
- Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis:
Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCs.
630-635
Poster Session 3
- Usama Malik, Oliver Diessel:
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs.
636-639
- Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki:
A Novel Toolset for the Development of FPGA-like Reconfigurable Logic.
640-643
- Ioannis Sourdis, Dionisios N. Pnevmatikatos, Stephan Wong, Stamatis Vassiliadis:
A Reconfigurable Perfect-Hashing Scheme for Packet Inspection.
644-647
- Yang Qu, Juha-Pekka Soininen, Jari Nurmi:
An Efficient Approach to Hide the Run-Time Reconfiguration from SW Applications.
648-653
- Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann:
An FPGA Network Architecture for Accelerating 3DES - CBC.
654-657
- K. Siozios, Konstantinos Tatas, George Koutroumpezis, D. J. Soudris, Adonios Thanailakis:
An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform.
658-661
- Boris Ratchev, Mike Hutton, David Mendel:
Coping With Uncertainty in FPGA Architecture Design.
662-665
- Naoki Iwanaga, Yuichiro Shibata, Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri:
Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA.
666-669
- Jean-Pierre Deschamps, Gustavo Sutter:
Finite Field Division Implementation.
670-674
- Philippe Faes, Mark Christiaens, Dries Buytaert, Dirk Stroobandt:
FPGA-Aware Garbage Collection in Java.
675-680
- Allen Michalski, Kris Gaj, Duncan A. Buell:
High-Throughput Reconfigurable Computing: A Design Study of an IDEA Encryption Cryptosystem on the SRC-6e Reconfigurable Computer.
681-686
- Nicolas Bruchon, Gaston Cambon, Lionel Torres, Gilles Sassatelli:
Magnetic remanent memory structures for dynamically reconfigurable fine grain FPGA.
687-690
- Kuen Hung Tsoi, Philip Heng Wai Leong:
Mullet - A Parallel Multiplier Generator.
691-694
- Martin Zádník, Tomas Pecenka, Jan Korenek:
NetFlow Probe Intended for High-Speed Networks.
695-698
- Zdenek Pohl, Premysl Sucha, Jiri Kadlec, Zdenek Hanzálek:
Performance Tuning of Iterative Algorithms in Signal Processing.
699-702
- Pascal Benoit, Jürgen Becker, Michel Robert, Lionel Torres, Gilles Sassatelli, Gaston Cambon:
Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors.
703-706
PhD Forum
- K. Siozios, Dimitrios Soudris, Adonios Thanailakis:
A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow.
707-708
- Frank Honoré:
A Power-Performance Scalable FPGA Using Configurable Voltage Domains and Design Mapping Tool.
709-710
- Luis E. Cordova, Duncan A. Buell:
An Approach to Scalable Molecular Dynamics Simulation Using Supercomputing Adaptive Processing Elements.
711-712
- Kuen Hung Tsoi:
Computer Arithmetic Synthesis Technologies on Reconfigurable Platforms.
713-714
- Chun Te Ewe:
Dual FiXed-point : An Efficient Alternative to Floating-point Computation for DSP applications.
715-716
- Florian Dittmann:
Efficient Execution on Reconfigurable Devices Using Concepts of Pipelining.
717-718
- Alastair M. Smith:
Exploration of Heterogeneous Reconfigurable Architectures.
719-720
- Fernando Pardo, P. López, Diego Cabello, M. Balsi:
FPGA Finite-Difference Time-Domain solver for thermal simulation.
721-722
- F. Javier Toledo, José-Javier Martínez, F. Javier Garrigós, José Manuel Ferrández de Vicente:
FPGA Implementation of an Augmented Reality Application for Visually Impaired People.
723-724
- Nicola Campregher:
FPGA Interconnect Fault tolerance.
725-726
- Kurian Oommen, David Harle:
Hardware Emulation of a Network on Chip Architecture based on a Clockwork Routed Manhattan Street Network.
727-728
- János Lazányi:
Instruction Set Extension Using Microblaze Processor.
729-730
- Lesley Shannon, Paul Chow:
Leveraging Reconfigurability in the Design Process.
731-732
- Martin J. Pearson:
MechanoProcessor: Modelling the Rodent Whisker Sensory System using FPGA.
733-734
- Rajarshee P. Bharadwaj:
Next Generation Architectures and CAD for Power Aware Programmable Fabrics.
735-738
- Renqiu Huang, Ranga Vemuri:
PAHLS: Towards Run-Time Synthesis for FPGAs.
739-740
- David Nguyen:
Reconfigurable Architectures for Real-Time Network Anomaly Detection.
741-742
- Hiren Joshi, S. S. Verma, G. K. Sharma:
Requested-QoS Driven Runtime Reconfiguration of Mobile Devices.
743-744
- Alexander Thomas:
Design of a Dynamic Reconfigurable Multi-Grained Hardware Architecture with Adaptive Runtime Routing.
745-746
- Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Testing Superscalar Processors in Functional Mode.
747-750
Copyright © Mon Nov 2 20:37:03 2009
by Michael Ley (ley@uni-trier.de)
