10. FPL 2000:
Villach,
Austria
Reiner W. Hartenstein, Herbert Grünbacher (Eds.):
Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings.
Lecture Notes in Computer Science 1896 Springer 2000, ISBN 3-540-67899-9 
@proceedings{DBLP:conf/fpl/2000,
editor = {Reiner W. Hartenstein and
Herbert Gr{\"u}nbacher},
title = {Field-Programmable Logic and Applications, The Roadmap to Reconfigurable
Computing, 10th International Workshop, FPL 2000, Villach, Austria,
August 27-30, 2000, Proceedings},
booktitle = {FPL},
publisher = {Springer},
series = {Lecture Notes in Computer Science},
volume = {1896},
year = {2000},
isbn = {3-540-67899-9},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Invited Keynotes
Network Processors
Prototyping
Dynamically Reconfigurable 1
Miscellaneous 1
Technology Mapping and Routing & Placement
- Srini Krishnamoorthy, Sriram Swaminathan, Russell Tessier:
Area-Optimized Technology Mapping for Hybrid FPGAs.
181-190
- Joerg Abke, Erich Barke:
CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs.
191-200
- Sushil Chandra Jain, Anshul Kumar, Shashi Kumar:
Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards.
201-210
- Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman:
A Placement Algorithm for FPGA Designs with Multiple I/O Standards.
211-220
- Holger Kropp, Carsten Reuter:
A Mapping Methodology for Code Trees onto LUT-Based FPGAs.
221-229
Biologically Inspired Methods
Invited Keynote
- Jan M. Rabaey:
Silicon Platforms for the Next Generation Wireless Systems - What Role Does Reconfigurable Hardware Play?
277-285
Invited Papers
- John S. McCaskill, Patrick Wagler:
From Reconfigurability to Evolution in Construction Systems: Spanning the Electronic, Microfluidic and Biomolecular Domains.
286-299
- Michel Renovell:
A Specific Test Methodology for Symmetric SRAM-Based FPGAs.
300-311
Mobile Communication
- Jürgen Becker, Thilo Pionteck, Manfred Glesner:
DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications.
312-321
- A. Blaickner, O. Nagy, Herbert Grünbacher:
Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Re-configurable Logic.
322-331
- Xavier Revés, Antoni Gelonch, Ferran Casadevall, José L. García:
Software Radio Reconfigurable Hardware System (SHaRe).
332-341
- Javier Ramírez, Antonio García, Pedro G. Fernández, Luis Parrilla, Antonio Lloris-Ruíz:
Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform.
342-351
Dynamically Reconfigurable 2
Design Space Exploration
- Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures.
389-399
- Paul M. Heysters, Jaap Smit, Gerard J. M. Smit, Paul J. M. Havinga:
Mapping of DSP Algorithms on Field Programmable Function Arrays.
400-411
- Darko Stefanovic, Margaret Martonosi:
On Availability of Bit-Narrow Operations in General-Purpose Applications.
412-421
- Radhika S. Grover, Weijia Shang, Qiang Li:
A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers.
422-431
- Frank Wolz, Reiner Kolla:
A New Floorplanning Method for FPGA Architectural Research.
432-442
Miscellaneous 2
Applications 1
- Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano:
A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems.
475-484
- Stephen J. Bellis, William P. Marnane:
A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System.
485-494
- Stephen J. Melnikoff, Philip James-Roxby, Steven F. Quigley, Martin J. Russell:
Reconfigurable Computing for Speech Recognition: Preliminary Findings.
495-504
- Hagen Ploog, Mathias Schmalisch, Dirk Timmermann:
Security Upgrade of Existing ISDN Devices by Using Reconfigurable Logic.
505-514
- Takahiro Miomo, Koichi Yasuoka, Masanori Kanazawa:
The Fastest Multiplier on FPGAs with Redundant Binary Representation.
515-524
Optimization
- Rolf Enzler, Tobias Jeger, Didier Cottet, Gerhard Tröster:
High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs.
525-534
- Russell Tessier, Heather Giza:
Balancing Logic Utilization and Area Efficiency in FPGAs.
535-544
- John M. Emmert, Charles E. Stroud, Jason A. Cheatham, Andrew M. Taylor, Pankaj Kataria, Miron Abramovici:
Performance Penalty for Fault Tolerance in Roving STARs.
545-554
- Jian Qiao, Makoto Ikeda, Kunihiro Asada:
Optimum Functional Decomposition for LUT-Based FPGA Synthesis.
555-564
- Michael Eisenring, Marco Platzner:
Optimization of Run-Time Reconfigurable Embedded Systems.
565-574
Invited Keynote
- Tom Kean:
It's FPL, Jim - But Not as We Know It! Opportunities for the New Commercial Architectures.
575-584
Invited Papers
Architectures
Methodology and Technology
Compilation and Related Issues
Applications 2
Short Papers
- Christian Siemers:
Reconfigurable Computing between Classifications and Metrics - The Approach of Space/Time-Scheduling.
769-772
- Winnie W. Cheng, Steven J. E. Wilton, Babak Hamidzadeh:
FPGA Implementation of a Prototype WDM On-Line Scheduler.
773-776
- Jens Hildebrandt, Dirk Timmermann:
An FPFA Based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard-Time Systems.
777-780
- Sergej Sawitzki, Jens Schönherr, Rainer G. Spallek, Bernd Straube:
Formal Verification of a Reconfigurable Microprocessor.
781-784
- Rafael Gadea Gironés, Vicente Herrero, Angel Sebastia, Antonio Mocholí Salcedo:
The Role of the Embedded Memories in the Implementation of Artificial Neural Networks.
785-788
- Guy Lecurieux Lafayette:
Programmable System Level Integration Brings System-on-Chip Design to the Desktop.
789-792
- A. Hilton, J. Hall:
On Applying Software Development Best Practice to FPFAs in Safety Critical Systems.
793-796
- Brandon Blodget:
Pre-route Assistant: A Routing Tool for Run-Time Reconfiguration.
797-800
- Tomoyoshi Kobori, Tsutomu Maruyama, Tsutomu Hoshino:
High Speed Computation of Lattice gas Automata with FPFA.
801-804
- Tsunemichi Shiozawa, Norbert Imlig, Kouichi Nagami, Kiyoshi Oguri, Akira Nagoya, Hiroshi Nakada:
An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture.
805-809
- Bogdan Matasaru, Tudor Jebelean:
FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers.
810-813
- Lukás Sekanina, Azeddien M. Sllame:
Toward Uniform Approach to Design of Evolvable Hardware Based Systems.
814-817
- Andrej Trost, Andrej Zemva, Baldomir Zajc:
Educational Programmable Hardware Prototyping and Verification System.
818-821
- Rolf Hoffmann, Bernd Ulmann, Klaus-Peter Völkmann, Stefan Waldschmidt:
A Stream Processor Architecture Based on the Configurable CEPRA-S.
822-825
- Uwe Hatnik, Jürgen Haufe, Peter Schwarz:
An Innovative Approach to Couple EDA Tools with Reconfigurable Hardware.
826-829
- Kalle Tammemäe, T. Evartson:
FPL Curriculum at Tallinn Technical University.
830-833
- Jean-Michel Raczinski, Stéphane Sladek:
The Modular Architecture of SYNTHUP, FPFA Based PCI Board for Real-Time Sound Synthesis and Digital Signal Processing.
834-837
- André Brinkmann, Dominik Langen, Ulrich Rückert:
A Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network Processor.
838-841
- Juanjo Noguera, Rosa M. Badia:
Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers.
842-845
- Chris Phillips:
Wireless Base Station Design Using a Reconfigurable Communications Processor.
846-848
- Erwan Fabiani, Dominique Lavenier:
Placement of Linear Arrays.
849-852
Copyright © Mon Nov 2 20:37:01 2009
by Michael Ley (ley@uni-trier.de)
