9. FPL 1999:
Glasgow,
UK
Patrick Lysaght, James Irvine, Reiner W. Hartenstein (Eds.):
Field-Programmable Logic and Applications, 9th International Workshop, FPL'99, Glasgow, UK, August 30 - September 1, 1999, Proceedings.
Lecture Notes in Computer Science 1673 Springer 1999, ISBN 3-540-66457-2 
Signal Processing
CAD Tools for DRL
Optimization Studies
Physical Design
Dynamically Reconfigurable Logic
Design Tools
Reconfigurable Computing
Applications
- Donald MacVicar, John W. Patterson, Satnam Singh:
Rendering Postscript Fonts on FPGAs.
223-232
- Stefan H.-M. Ludwig, Robert Slous, Satnam Singh:
Implementing Photoshop Filters in Virtex.
233-242
- Klaus Feske, Michael Scholz, Günther Döring, Denis Nareike:
Rapid FPGA Prototyping of a DAB Test Data Generator Using Protocol Compiler.
243-252
- Nabeel Shirazi, Wayne Luk, Dan Benyamin, Peter Y. K. Cheung:
Quantitative Analysis of Run-Time Reconfigurable Database Search.
253-263
Novel Architectures
Machine Applications
Short Papers
- Holger Kropp, Carsten Reuter, Matthias Wiege, Tien-Toan Do, Peter Pirsch:
An FPGA-based Prototyping System for Real-Time Verification of Video Processing Schemes.
333-338
- Tomas Dulik:
An FPGA Implementation of Goertzel Algorithm.
339-346
- Mathew Wojko:
Pipelined Multipliers and FPGA Architectures.
347-352
- Emanuel M. Popovici, Patrick Fitzpatrick, Colin C. Murphy:
FPGA Design Trade-Offs for Solving the Key Equation in Reed-Solomon Decoding.
353-358
- Juri Põldre, Kalle Tammemäe:
Reconfigurable Multiplier for Virtex FPGA Family.
359-364
- Iakovos Stamoulis, Martin White, Paul F. Lister:
Pipelined Floating Point Arithmetic Optimized for FPGA Architectures.
365-370
- Samuel Holmström:
SL - A Structural Hardware Design Language.
371-376
- R. Bruce Maunder, Zoran A. Salcic, George G. Coghill:
High-Level Hierachical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules.
377-384
- Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
Mapping Applications onto Reconfigurable Kress Arrays.
385-390
- Martin Danek, Zdenek Muzikár:
Global Routing Models.
391-395
- Andrés D. García, Wayne P. Burleson, Jean-Luc Danger:
Power Modelling in Field Programmable Gate Arrays (FPGA).
396-404
- Dinesh Bhatia, Kuldeep S. Simha, PariVallal Kannan:
NEBULA: A Partially and Dynamically Reconfigurable Architecture.
405-410
- Keith J. Symington, John F. Snowdon, Heiko Schroeder:
High Bandwidth Dynamically Reconfigurable Architectures Using Optical Interconnects.
411-416
- Torsten Kuberka, Andreas Kugel, Reinhard Männer, Holger Singpiel, R. Spurzem, R. Klessen:
AHA-GRAPE: Adaptive Hydrodynamic Architecture-GRAvity PipE.
417-424
- Malachy Devlin, Allan J. Cantle:
DIME - The First Module Standard for FPGA Based High Performance Computing.
425-430
- Michael Dales:
The Proteus Processor - A Conventional CPU with Reconfigurable Functionality.
431-437
- Valeri F. Tomashau:
Logic Circuit Speeding up through Multiplexing.
438-443
- Philip James-Roxby, Elena Cerro-Prada:
A Wildcarding Mechanism for Acceleration of Partial Configurations.
444-449
- Tsutomu Maruyama, Masaaki Takagi, Tsutomu Hoshino:
Hardware Implementation Techniques for Recursive Calls and Loops.
450-455
- Juanjo Noguera, Rosa M. Badia, Jordi Domingo-Pascual, Josep Solé-Pareta:
A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation.
456-461
- María Dolores Valdés, María José Moure, Enrique Mandado, Angel Salaverría:
An Alternative Solution for Reconfigurable Coprocessors Hardware and Interface Synthesis.
462-468
- Abdellah Touhafi, Wouter Brissinck, Erik F. Dirkx:
Reconfigurable Programming in the Large on Extendable Uniform Reconfigurable Computing Array's: An Integrated Approach Based on Reconfigurable Virtual Architectures.
469-474
- Sergej Sawitzki, Rainer G. Spallek:
A Concept for an Evaluation Framework for Reconfigurable Systems.
475-480
- Rainer Kress, Andreas Pyttel:
Debugging Application-Specific Programmable Products.
481-486
- Steve Casselman, John Schewel, Christophe Beaumont:
IP Validation for FPGAs Using Hardware Object Technology.
487-494
- Matthias Böge, Andreas Koch:
A Processor for Artificial Life Simulation.
495-500
- Craig Slorach, Steve Fulton, Ken Sharman:
A Distributed, Scalable, Multi-layered Approach to Evolvable System Design Using FPGAs.
501-506
- Tri Caohuu, Thuy Trong Le, Manfred Glesner, Jürgen Becker:
Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching.
507-513
- Tsutomu Maruyama, Tsutomu Hoshino:
A Reconfigurable Architecture for High Speed Computation by Pipeline Processing.
514-519
- Bernardo Kastrup, Jef L. van Meerbergen, Katarzyna Nowak:
Seeking (the right) Problems for the Solutions of Reconfigurable Computing.
520-525
- Wong Hiu Yung, Wing Seung Yuen, Kin-Hong Lee, Philip Heng Wai Leong:
A Runtime Reconfigurable Implementation of the GSAT Algorithm.
526-531
- Kolja Sulimma, Dominik Stoffel, Wolfgang Kunz:
Accelerating Boolean Implications with FPGAs.
532-537
Copyright © Mon Nov 2 20:37:01 2009
by Michael Ley (ley@uni-trier.de)
