16. FPGA 2008: Monterey, CA, USA

Workshop

• Guy G. Lemieux, Tarek A. El-Ghazawi:
  Designing with extreme parallelism. 1-2
  

Physical design

• Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal:
  Architecture-specific packing for virtex-5 FPGAs. 5-13
  
• Adrian Ludwin, Vaughn Betz, Ketan Padalia:
  High-quality, deterministic parallel placement for FPGAs on commodity hardware. 14-23
  
• Keith So:
  Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals. 24-34
  

Technology mapping

• Michael T. Frederick, Arun K. Somani:
  Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs. 37-46
  
• Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko:
  WireMap: FPGA technology mapping for improved routability. 47-55
  
• Kirill Minkovich, Jason Cong:
  Mapping for better than worst-case delays in LUT-based FPGA designs. 56-64
  

Simulation acceleration

• Jason Cong, Yi Zou:
  Lithographic aerial image simulation with FPGA-based hardwareacceleration. 67-76
  
• Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai:
  A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. 77-86
  
• Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer:
  A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. 87-96
  

Synthesis at higher-level abstractions

• Quang Dinh, Deming Chen, Martin D. F. Wong:
  Efficient ASIP design for configurable processors with fine-grained resource sharing. 99-106
  
• Jason Cong, Wei Jiang:
  Pattern-based behavior synthesis for FPGA resource reduction. 107-116
  
• Scott Sirowy, Greg Stitt, Frank Vahid:
  C is for circuits: capturing FPGA circuits as sequential code for portability. 117-126
  

Panel

• Tarek A. El-Ghazawi, Guy G. Lemieux:
  Extreme parallel architectures for the masses. 127-128
  

Architecture tools

• Mingjie Lin, Abbas El Gamal:
  TORCH: a design tool for routing channel segmentation in FPGAs. 131-138
  
• Wei Mark Fang, Jonathan Rose:
  Modeling routing demand for early-stage FPGA architecture development. 139-148
  
• Ian Kuon, Jonathan Rose:
  Area and delay trade-offs in the circuit and architecture design of FPGAs. 149-158
  
• Lerong Cheng, Yan Lin, Lei He:
  Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. 159-168
  

Architecture

• Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
  A novel FPGA logic block for improved arithmetic performance. 171-180
  
• Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne:
  Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. 181-190
  
• Mingjie Lin:
  The amorphous FPGA architecture. 191-200
  

Reconfigurable computing

• Narges Bani Asadi, Teresa H. Y. Meng, Wing H. Wong:
  Reconfigurable computing for learning Bayesian networks. 203-211
  
• John H. Kelm, Steven S. Lumetta:
  HybridOS: runtime support for reconfigurable accelerators. 212-221
  
• Jason Yu, Guy Lemieux, Christopher Eagleston:
  Vector processing as a soft-core CPU accelerator. 222-232
  

Random number generators

• David B. Thomas, Wayne Luk:
  FPGA-optimised high-quality uniform random number generators. 235-244
  
• Ishaan L. Dalal, Deian Stefan:
  A hardware framework for the fast generation of multiple long-period random number streams. 245-254
  

Poster session 1: architecture and CAD

• Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley:
  Efficient tiling patterns for reconfigurable gate arrays. 257
  
• Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong:
  FPGA interconnect design using logical effort. 257
  
• Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera:
  Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs. 257
  
• Paul E. McKechnie, Nathan A. Lindop, Wim Vanderbauwhede:
  A type system for static typing of a domain-specific language. 258
  
• N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung:
  Measuring and modeling FPGA clock variability. 258
  
• Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
  High-throughput interconnect wave-pipelining for global communication in FPGAs. 258
  
• Matthew Collin Jordan, Ramachandran Vaidyanathan:
  Configurable decoders with application in fast partial reconfiguration of FPGAs. 259
  

Poster session 2: computing with reconfigurable technology

• Florent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran:
  When FPGAs are better at floating-point than microprocessors. 260
  
• Xiaojun Wang, Miriam Leeser:
  Efficient FPGA implementation of qr decomposition using a systolic array architecture. 260
  
• Kevin Camera, Robert W. Brodersen:
  An integrated debugging environment for FPGA computing platforms. 260
  
• Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan:
  CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures. 261
  
• Hidenori Matsubayashi, Shinsuke Nino, Toru Aramaki, Yuichiro Shibata, Kiyoshi Oguri:
  Retrieving 3-d information with FPGA-based stream processing. 261
  
• Maryam Moazeni, Alireza Vahdatpour, Karthik Gururaj, Majid Sarrafzadeh:
  Communication bottleneck in hardware-software partitioning. 262
  

Poster session 3: applications and implementations

• Luis Miguel Contreras-Medina, René de Jesús Romero-Troncoso, Jose de Jesus Rangel-Magdaleno, Jesus Roberto Millan-Almaraz:
  FPGA based multiple-channel vibration analyzer for industrial applications with reconfigurable post-processing capabilities for automatic failure detection on machinery. 263
  
• Jose de Jesus Rangel-Magdaleno, René de Jesús Romero-Troncoso, Luis Miguel Contreras-Medina, Arturo Garcia-Perez:
  FPGA implementation of a novel algorithm for on-line bar breakage detection on induction motors. 263
  
• Atul Mahajan, Benfano Soewito, Sai K. Parsi, Ning Weng, Haibo Wang:
  Implementing high-speed string matching hardware for network intrusion detection systems. 264
  
• Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck:
  Fpga-based data acquisition system for a positron emission tomography (PET) scanner. 264
  
• David Sheldon, Frank Vahid:
  A pipelined binary tree as a case study on designing efficient circuits for an FPGA in a bram aware design. 264
  
• Jean-Baptiste Note, Éric Rannaud:
  From the bitstream to the netlist. 264
  
• Amin Ansari, Keyvan Amiri:
  Flexible FPGA-based parallel architecture for identification of repetitive sequences in interleaved pulse trains. 265