25. EUROMICRO 1999:
Milan,
Italy
25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy.
IEEE Computer Society 1999, ISBN 0-7695-0321-7 
@proceedings{DBLP:conf/euromicro/1999,
title = {25th EUROMICRO '99 Conference, Informatics: Theory and Practice
for the New Millenium, 8-10 September 1999, Milan, Italy},
booktitle = {EUROMICRO},
publisher = {IEEE Computer Society},
year = {1999},
isbn = {0-7695-0321-7},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Volume I
Workshop on Digital System Design:
Architectures,
Methods and Tools
- Lech Józwiak:
Digital System Design: Architectures, Methods and Tools.
1004-
Keynote
System Architecture Exploration
Special Architectures Poster Session
- Ki Leung, Adam Postula:
Specialized Processor for Channel Allocation in a Cellular Mobile Network.
1038-1041
- Kimmo Kuusilinna, Pasi Liimatainen, Timo Hämäläinen, Jukka Saarinen:
Reconfiguration Mechanism for an IP Block Based Interconnection.
1042-1045
- Mathias Kortke, Dirk Fimmel, Renate Merker:
Parallelization of Algorithms for a System of Digital Signal Processors.
1046-1050
- Claudio Sansoè, Francesco Gregoretti, Leonardo Maria Reyneri:
A Neuro-Fuzzy Real-Time Image Processing System.
1051-1056
- C. John Glossner, Stamatis Vassiliadis:
Delft-Java Dynamic Translation.
1057-1062
- Javier Hormigo, Julio Villalba, Emilio L. Zapata:
Arithmetic Unit for the Computation of Interval Elementary Functions.
1063-1066
- Gil-Haeng Lee:
Issues of the State Information for Location and Information Policies in Distributed Load Balancing Algorithm.
1067-1070
- Jose Antonio Boluda, Fernando Pardo, Francisco Blasco, Joan Pelechano:
A Pipelined Reconfigurable Architecture for Visual-Based Navigation.
1071-1074
- Jens Schönherr, Ingo Schreiber, Eva Fordran, Bernd Straube:
Hazard Checking in Pipelined Processor Designs Using Symbolic Model Checking.
1075-
Logic Synthesis for FPGAs and CLPDs
Special Architectures
- Rong Lin, Kevin E. Kerr, André S. Botha:
A Novel Approach for CMOS Parallel Counter Design.
1112-1119
- Gloria Martínez, Germán Fabregat, Vicente Hernández:
A Systolic Library for Solving Matrix Equations.
1120-1125
- Jose Luis Nunez, Claudia Feregrino, Simon Jones, Stephen Bateman:
The X-MatchLITE FPGA-Based Data Compressor.
1126-1132
- Alexander Schwarz, Bärbel Mertsching, M. Brucke, Wolfgang Nebel, Jürgen Tchorz, Birger Kollmeier:
Implementing a Quantitative Model for the "Effective" Signal Processing in the Auditory System on a Dedicated Digital VLSI Hardware.
1133-1139
- Kees-Jan Van der Kolk, Ed F. Deprettere, Jeong-A. Lee:
A Floating Point Vectoring Algorithm Based on Fast Rotations.
1140-
Logic Synthesis for FPGAs
CPU and Memory Architectures I
Specification and Modeling
- Asheesh Khare, Nicolae Savoiu, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau:
V-SAT: A Visual Specification and Analysis Tool for System-On-Chip Exploration.
1196-1203
- Gregorio Cappuccino, Giuseppe Cocorullo:
A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines.
1204-1208
- M. A. Sacristán, María Victoria Rodellar Biarge, A. Diaz, V. Garcia, Pedro Gómez Vilda:
A Reusable Inner Product Unit for DSP Applications.
1209-1213
- Frédéric Mallet, Fernand Boéri:
Esterel and Java in an Object-Oriented Modelling and Simulation Framework for Heterogeneous Software and Hardware Systems The SEP Approach.
1214-
CPU and Memory Architectures Poster Session
- Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim:
A Selective Compressed Memory System by On-Line Data Decompressing.
1224-1227
- Li-San Li, Huang-Zhen Chun:
Lookahead Cache with Instruction Processing Unit for Filling Memory Gap.
1228-1231
- Øyvind Strøm, Audun Klauseie, Einar J. Aas:
A Study of Dynamic Instruction Frequencies in Byte Compiled Java Programs.
1232-1235
- Tomás Bautista, Antonio Núñez:
Design of Efficient SPARC Cores for Embedded Systems.
1236-1239
- Rolf Hakenes, Yiannos Manoli:
A Segmented Gray Code for Low-Power Microcontroller Address Buses.
1240-1243
- Alessandro De Gloria, Paolo Palma, Mauro Olivieri:
Delay-Insensitive Synthesis of the MCS 251 Microcontroller Core for Low Power Applications.
1244-1247
- Jochen Kreuzinger, Theo Ungerer:
Context-Switching Techniques for Decoupled Multithreaded Processors.
1248-
Testing and Verification
Logic and High Level Synthesis Poster Session
Embedded System Optimization and Prototyping
Reconfigurable Architectures
Decision Diagrams,
Decomposition and Optimization
Specification and Modeling Poster Session
- F. Muller, Jean Paul Calvez, Dominique Heller, Olivier Pasquier:
An Interactive Modeling and Generation Tool for the Design of Hw/Sw Systems.
1382-1385
- S. Barrios, J. López:
Heterogeneous Systems Design: A UML-Based Approach.
1386-1387
- Young Moo Lee, Kyu Ho Park:
Unified Modeling Graph for Specifying and Synthesizing Chip-Level Interfaces.
1388-1389
- Francesco Curatelli, Leonardo Mangeruca, Marco Chirico:
A Message-Passing Communication Scheme for System Specification.
1390-1393
- Claus Schneider:
Executable Specification for Multimedia Supporting Refinement and Architecture Exploration.
1394-1397
- Mathias Sporer, Karlheinz Agsteiner, Dieter Monjau, Michael Schwaar:
Knowledge Based Specification and Modeling of Embedded Systems.
1398-1401
- Siddika Berna Örs, Ahmet Dervisoglu:
Modeling Bit Multiplication Blocks for DSP Applications Using VHDL.
1402-1405
- Eiichirou Shigehara, Yoshinori Takeuchi, Masaharu Imai, Tsutomu Kimura:
Application of FHM-Based Design Method to Scalable 2-D DCT Processor.
1406-1409
- Grzegorz Kucharski, Wlodzimierz Wrona:
An Optimization of Simulation Time in the Hardware Accelerated VLSI Simulator.
1410-
CPU and Memory Architectures 2
System Synthesis and Validation Poster Session
- B. S. Visser:
A Framework for Retargetable Code Generation Using Simulated Annealing.
1458-1462
- Leo J. van Bokhoven, Jeroen Voeten, Marc Geilen:
Software Synthesis for System Level Design Using Process Execution Trees.
1463-1467
- Gregor Polansek, Andrej Zemva, Andrej Trost:
HW/SW Co-Simulation of Target C++ Applications and Synthesizable HDL with Performance Estimation.
1468-1471
- Francisco Moya, Juan Carlos López, José Manuel Moya:
Evaluation of Design Space Exploration Strategies.
1472-1476
- Matthias Bauer, Wolfgang Ecker, Renate Henftling, Andreas Zinn:
A Method for Accelerating Test Environments.
1477-1480
- Janusz Sosnowski, Piotr Gawkowski:
Tracing Fault Effects in System Environment.
1481-1486
- Pierre Wodey, Fabrice Baray:
Linking Codesign and Verification by Means of E-LOTOS FDT.
1487-1491
- Christian Kreiner, Christian Steger, Reinhold Weiss:
A Hardware/Software Cosimulation Environment for DSP Applications.
1492-1495
- P. H. A. van der Putten, Jeroen Voeten, Marc Geilen, M. P. J. Stevens:
System Level Models for Real-Time Communication.
1496-
High Level Synthesis
Volume II
Keynote
- J. Sundberg:
Music Technology and Audio Processing: Rall. or Accel. into the Millennium?
1-
Workshop on Music Technology and Audio Processing
- David M. Howard:
Workshop Chair Introduction: Music Technology and Audio Processing.
2004-
Music Performance Issues
Music Education
Audio Signal Processing
Synthesising Singing Ensemble
Acoustic Modelling
- David M. Howard:
Digital Waveguide Modelling of Room Acoustics: Comparing Mesh Topologies.
2082-
Workshop on Dependable Computing Systems
- Julian M. Bass:
Workshop Chair Introduction: Dependable Computing Systems.
2094-
Keynote
- Bev Littlewood:
Two Heads Are Better Than One: Using Diversity to Make Software Dependable.
15-
Recovery and Masking Techniques
Future Perspectives and Industrial Practice
Short Presentations
Workshop on Software Process and Product Improvement
- Gerhard Ghroust:
Workshop Chair Introduction: Software Process and Product Improvement.
2158-
Keynote
- Matjaz Mulej:
The Law of Requisite Holism Systemic versus Reductionistic versus Complex Thinking.
27-
The Software Industry - State of the Art
- Yingxu Wang, Graham King, Hakan Wickberg, Alec Dorling:
What the Softward Industry Says about the Practices Modelled in Current Softward Process Models?
2162-
- G. Magnani:
The Role of the Improvement Manager. Critical Factors Affecting the Development of an Improvement Strategy: Leadership, Organization, Key-Process or Business Results?
29-
Successful Software Process Improvements
Tool Support for Development Activities
Object Oriented Approaches
Managing Requirements
Measuring the Software Process
Improving Software Product Quality
Workshop on Multimedia and Telecommunications
Multimedia Architectures
Protocols
Performance Evaluations
Image Processing
Applications and Security
Special Session on Network Computing
Special Session on Network Computing I
Special Session on Network Computing II
Copyright © Mon Nov 2 20:35:16 2009
by Michael Ley (ley@uni-trier.de)
