ERSA 2007:
Las Vegas,
Nevada,
USA
Toomas P. Plaks (Ed.):
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2007, Las Vegas, Nevada, USA, June 25-28, 2007.
CSREA Press 2007, ISBN 1-60132-026-4 
Keynotes and Invited Talks
Reconfigurable Systems on Chip
- Swathi Tanjore Gurumani, B. Earl Wells:
Energy-Efficient Dynamic Task Scheduling Algorithm for Reconfigurable System-on-Chip Architectures.
37-43
- Erik Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, David L. Andrews:
Memory Hierarchy for MCSoPC Multithreaded Systems.
44-50
- Pranav Vaidya, Jaehwan John Lee:
Design Space Exploration of Multiprocessor Systems with MultiContext Reconfigurable Co-Processors.
51-60
- Xiaofang Wang, Sotirios G. Ziavras, Jie Hu:
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors.
61-70
Task Scheduling and Dynamic Reconfiguration
- Javier Resano, Juan Antonio Clemente, Carlos Gonzalez, Jose Luis Garcia, Daniel Mozos:
HW implementation of an execution manager for reconfigurable systems.
71-77
- Matteo Giani, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto:
Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity.
78-84
- Fredy Rivera, Marcos Sanchez-Elez, Nader Bagherzadeh:
Configuration and Data Scheduling for Executing Dynamic Applications onto Multi-Context Reconfigurable Architectures.
85-91
- Darrin M. Hanna, Michael DuChene, Lawrence Kennedy, Brian Carpenter:
A Compiler to Generate Hardware from Java Byte Codes for High Performance, Low Energy Embedded Systems.
92-98
- Wei-Ting Wang, Wai-Hong Tam, Yi-Chi Chen, Kuen-Cheng Chiang, Chung-Ping Chung:
Selecting Heterogeneous Computation Blocks for Reconfigurable JPEG Codec Computing.
99-106
Applications
- Chuan He, Guan Qin, Richard E. Ewing, Wei Zhao:
High-Precision BLAS on FPGA-enhanced Computers.
107-116
- Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Wayne Burleson:
High-efficiency protection solution for off-chip memory in embedded systems.
117-123
- Eric Grobelny, Casey Reardon, Adam Jacobs, Alan D. George:
Simulation Framework for Performance Prediction in the Engineering of Reconfigurable Systems and Applications.
124-130
- Michaela Amoo, Clay Gloster:
FPGA Implementation of an Analytical Design Method for A Cycle-Optimal 2D-DCT/IDCT.
131-137
- Abdel Ejnioui:
Prototyping of a Two-Phase Micropipeline on FPGAs.
138-146
Reconfigurable Hardware
- Weinan Chen, Chenglian Peng, Bo Zhou:
A New Routing Approach to Minimizing FPGA Reconfiguration Data.
147-151
- Florian Dittmann, Achim Rettberg, Raphael Weber:
Latency Optimization for a Reconfigurable, Self-Timed, and Bit-Serial Architecture.
152-158
- Sam Lee, Paul Chow:
An FPGA Implementation of Reciprocal Sums for SPME.
159-165
- Melissa Smith, Gregory Peterson:
Optimization of Shared High-Performance Reconfigurable Computing Resources.
166-174
- Christophe Wolinski, Krzysztof Kuchcinski:
Computation Patterns Identification for Instruction Set Extensions Implemented as Reconfigurable Hardware.
175-181
- Jason Meyer, Fatih Kocan, Daniel G. Saab:
Critical Path Delay Reduction in FPGAs with Unbalanced Lookup Times.
182-190
Short Papers
- Elena Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor:
Reducing the reconfiguration overhead: a survey of techniques.
191-194
- Henrik Svensson, Thomas Lenart, Viktor Öwall:
Implementing the G.723.1 Speech Codec Using a Coarse-Grained Reconfigurable Coprocessor.
195-198
- Cristiana Bolchini, Fabio Salice, Marco D. Santambrogio:
Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs.
199-202
- Vu Manh Tuan, Yohei Hasegawa, Hideharu Amano:
Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor.
203-206
- Pekka Rantala, Jouni Isoaho, Hannu Tenhunen:
Agent-Based Reconfigurability for Fault-Tolerance in Network-on-Chip.
207-210
- Dimitris Syrivelis, Spyros Lalis:
Design and Evaluation of a Software Infrastructure for the Runtime Management of Reconfigurable Resources.
211-215
- Anna Antola, Marco Castagna, Pamela Gotti, Marco D. Santambrogio:
Evolvable Hardware: A Functional Level Evolution Framework Based on ImpulseC.
216-219
- Neil Steiner, Peter Athanas:
Autonomous Computing Systems: A Proposed Roadmap.
220-226
Posters
Late Papers
- Yong-Kyu Jung:
Pure ASIC-Based Retargetable Computing: Architectures, Advantages, and Challenges.
231-237
- Jens Hagemeyer, Boris Kettelhoit, Markus Koester, Mario Porrmann:
Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs.
238-247
- Alex Marschner, Stephen D. Craven, Peter M. Athanas:
A Sandbox for Exploring the OpenFire Processor.
248-251
- Arjun K. Pai, Khaled Benkrid:
Power Efficient Domain-Specific Reconfigurable Architectures for System-on-Chip Applications.
252-258
- Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi:
272 Gate Count Optically Differential Reconfigurable Gate Array VLSI.
259-264
- Ludek Bryan, Otto Fucík:
FPGA Implementation of a Reconfigurable License Plate Detection Method.
265-268
- Rawad N. Al-Haddad, Carthik A. Sharma, Ronald F. DeMara:
Performance Evaluation of Two Allocation Schemes for Combinatorial Group Testing Fault Isolation.
269-272
- Jeoong Sung Park, Hong-Jip Jung:
Efficient FPGA-based Implementation of Time Synchronization for MIMO-OFDM.
273-279
- Stephen D. Craven, Peter M. Athanas:
High-Level Specification of Runtime Reconfigurable Designs.
280-283
- Ross Brennan, Michael Manzke, Keith O'Conor, John Dingliana, Carol O'Sullivan:
A Scalable and Reconfigurable Shared-Memory Graphics Cluster Architecture.
284-290
- Minoru Watanabe:
Optimization of Reconfiguration-speed Control Bits for an Optically Reconfigurable Gate Array.
291-294
- Sébastien Lafontant, Tarek Taha:
Feasibility of Hardware Acceleration of a Neocortex Model.
295-301
- Neil Steiner, Peter M. Athanas:
Autonomous Computing Systems: A Proof-of-Concept.
302-
Copyright © Mon Nov 2 20:34:26 2009
by Michael Ley (ley@uni-trier.de)
