ED&TC 1997: Paris, France

System Analysis Techniques and Applications

• Ali Dasdan, Anmol Mathur, Rajesh K. Gupta:
  RATAN: A tool for rate analysis and rate constraint debugging for embedded systems. 2-6
  
• Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau:
  Efficient utilization of scratch-pad memory in embedded processor applications. 7-11
  
• Pierre Girodias, Eduard Cerny:
  Interface timing verification with delay correlation using constraint logic programming. 12-19
  

Sequential ATPG

• Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
  Sequential circuit test generation using dynamic state traversal. 22-28
  
• A. Dargelas, C. Gauthron, Yves Bertrand:
  MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits. 29-36
  
• Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
  New static compaction techniques of test sequences for sequential circuits. 37-43
  

Design and Design Methodology for Analog Circuits

• Philippe Bénabès, Mansour Keramat, Richard Kielbasa:
  A methodology for designing continuous-time sigma-delta modulators. 46-50
  
• Guo-Neng Lu, Gerard Sou:
  A CMOS low-voltage, high-gain op-amp. 51-55
  
• Stéphane Donnay, Georges G. E. Gielen, Willy M. C. Sansen, Wim Kruiskamp, Domine Leenaerts, W. van Bokhoven:
  High-level synthesis of analog sensor interface front-ends. 56-60
  

Advances in Built-In Self-Test

• Mehrdad Nourani, Christos A. Papachristou:
  Structural BIST insertion using behavioral test analysis. 64-68
  
• Christian Dufaza, Yervant Zorian:
  On the generation of pseudo-deterministic two-patterns test sequence with LFSRs. 69-76
  
• Dimitrios Kagaris, Spyros Tragoudas:
  Cellular automata for generating deterministic test sequences. 77-81
  

Synthesis of Controllers

• Andre Hertwig, Hans-Joachim Wunderlich:
  Fast controllers for data dominated applications. 84-89
  
• Kazuo Iwama, Kensuke Hino, Hiroyuki Kurokawa, Sunao Sawada:
  Random benchmark circuits with controlled attributes. 90-97
  
• Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev:
  Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis. 98-105
  

Microsystems Design I

• Klaus Hofmann, Manfred Glesner, Nicu Sebe, A. Manolescu, Santiago Marco, Josep Samitier, Jean-Michel Karam, Bernard Courtois:
  Generation of the HDL-A-model of a micromembrane from its finite-element-description. 108-112
  
• S. Wünsche, C. Clauss, P. Schwarz, Frank Winkler:
  Microsystem design using simulator coupling. 113-118
  
• B. Romanowicz, M. Laudon, P. Lerch, P. Renaud, Hans Peter Amann, A. Boegli, Vincent Moser, Fausto Pellandini:
  Modeling and simulation of electromechanical transducers in microsystems using an analog hardware description language. 119-123
  

Software Generation for Embedded Processors

• M. L. G. Smeets, Emile H. L. Aarts, Gerben Essink, Erwin A. de Kock:
  Delay management for programmable video signal processors. 126-133
  
• Yanbing Li, Wayne Wolf:
  Hierarchical scheduling and allocation of multirate systems on heterogeneous multiprocessors. 134-139
  
• Rainer Leupers, Peter Marwedel:
  Retargetable generation of code selectors from HDL processor models. 140-144
  

Register Transfer Level Test Synthesis

• Subhrajit Bhattacharya, Sujit Dey, Bhaskar Sengupta:
  An RTL methodology to enable low overhead combinational testing. 146-152
  
• Xinli Gu, Erik Larsson, Krzysztof Kuchcinski, Zebo Peng:
  A controller testability analysis and enhancement technique. 153-157
  
• Marie-Lise Flottes, R. Pires, Bruno Rouzeyre:
  Analyzing testability from behavioral to RT level. 158-165
  

BDDs and Formal Verification

• Andreas Hett, Rolf Drechsler, Bernd Becker:
  Fast and efficient construction of BDDs by reordering based synthesis. 168-175
  
• Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer:
  Verification and synthesis of counters based on symbolic techniques. 176-181
  
• Thomas Kropf, Jürgen Ruf:
  Using MTBDDs for discrete timed symbolic model checking. 182-187
  

Microsystems Design II

• J. P. Fradin, L. Molla, B. Desaunettes:
  Analysis of 3D conjugate heat transfers in electronics. 190-194
  
• Ronald J. W. T. Tangelder, G. Diemel, Hans G. Kerkhoff:
  Smart sensor system application: an integrated compass. 195-199
  
• M. Lang, D. David, Manfred Glesner:
  Automatic transfer of parametric FEM models into CAD-layout formats for top-down design of microsystems. 200-204
  

High Performance Architectures for Multimedia and Communication ASICs

• Radim Cmar, Serge Vernalde:
  Highly scalable parallel parametrizable architecture of the motion estimator. 208-212
  
• Ander Royo, Javier Moran, Juan Carlos López:
  Design and implementation of a coprocessor for cryptography applications. 213-217
  
• J. Riesco, J. C. Diaz, L. A. Merayo, J. L. Conesa, C. Santos, E. Juarez:
  On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASIC. 218-222
  

Decision Diagrams and Diagnosis

• Olivier Coudert:
  Solving graph optimization problems with ZBDDs. 224-228
  
• Christoph Scholl, S. Melchior, Günter Hotz, Paul Molitor:
  Minimizing ROBDD sizes of incompletely specified Boolean functionsby exploiting strong symmetries. 229-234
  
• Ayman M. Wahba, Dominique Borrione:
  Connection error location and correction in combinational circuits. 235-241
  

Performance Modeling

• John P. Fishburn:
  Shaping a VLSI wire to minimize Elmore delay. 244-251
  
• Sandip Kundu, Uttam Ghoshal:
  Inductance analysis of on-chip interconnects [deep submicron CMOS]. 252-255
  
• U. Geigenmüller, N. P. van der Meijs:
  Cartesian multipole based numerical integration for 3D capacitance extraction. 256-259
  

Progress in IDDQ Test Technology

• Viera Stopjaková, Hans A. R. Manhaeve:
  CCII+ current conveyor based BIC monitor for I_DDQ testing of complex CMOS circuits. 266-270
  
• M. Sachdev:
  Deep sub-micron I_DDQ testing: issues and solutions. 271-278
  
• B. Laquai, H. Richter, H. Werkmann:
  A production-oriented measurement method for fast and exhaustive Iddq tests. 279-286
  

Architecture Exploration

• Pradip K. Jha, Nikil D. Dutt:
  Library mapping for memories. 288-292
  
• Miguel Miranda, M. Kaspar, Francky Catthoor, Hugo De Man:
  Architectural exploration and optimization for counter based hardware address generation. 293-298
  
• Min Xu, Fadi J. Kurdahi:
  RTL synthesis with physical and controller information. 299-303
  

Layout Design

• K. S. Seong, C. M. Kyung:
  Two-way partitioning based on direction vector [layout design]. 306-310
  
• Le-Chin Eugene Liu, Carl Sechen:
  Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic. 311-318
  
• Hsiao-Ping Tseng, Carl Sechen:
  A gridless multi-layer router for standard cell circuits using CTM cells. 319-326
  

Testability Solutions for Regular Structures

• Kanad Chakraborty, Pinaki Mazumder:
  A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs. 330-334
  
• Ricardo de Oliveira Duarte, Michael Nicolaidis, Hakim Bederr, Yervant Zorian:
  Fault-secure shifter design: results and implementations. 335-341
  
• Chih-Tsun Huang, Cheng-Wen Wu:
  High-speed C-testable systolic array design for Galois-field inversion. 342-346
  

Data Converter Test Issues

• Karim Arabi, Bozena Kaminska:
  Efficient and accurate testing of analog-to-digital converters using oscillation-test method. 348-352
  
• R. de Vries, Taco Zwemstra, E. M. J. G. Bruls, Paul P. L. Regtien:
  Built-in self-test methodology for A/D converters. 353-358
  
• E. K. F. Lee:
  Reconfigurable data converter as a building block for mixed-signal test. 359-363
  

Extensions and Acceleration of Discrete Event Simulation

• Peter Walker, Sumit Ghosh:
  VHDL extensions for complex transmission line simulation. 368-372
  
• Minoru Shoji, Fumiyasu Hirose, Shintaro Shimogori, Satoshi Kowatari, Hiroshi Nagai:
  Acceleration of behavioral simulation on simulation specific machines. 373-377
  
• Peter Walker, Sumit Ghosh:
  Exploiting temporal independence in distributed preemptive circuit simulation. 378-382
  

Analog Design and Layout Tools

• Les T. Walczowski, D. Nalbantis, W. A. J. Waller, Keng-Hua Shi:
  Analogue layout generation by World Wide Web server-based agents. 384-388
  
• Juan A. Prieto, Adoración Rueda, José M. Quintana, José Luis Huertas:
  A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs. 389-394
  
• Ignacio Garcia-Vargas, Mariano Galan, Francisco V. Fernández, Ángel Rodríguez-Vázquez:
  An algorithm for numerical reference generation in symbolic analysis of large analog circuits. 395-399
  

Power Modeling and Estimation

• Alessandro Bogliolo, Luca Benini, Giovanni De Micheli:
  Adaptive least mean square behavioral power modeling. 404-410
  
• Sergey Gavrilov, Alexey Glebov, S. Rusakov, David Blaauw, Larry G. Jones, Gopalakrishnan Vijayan:
  Fast power loss calculation for digital static CMOS circuits. 411-415
  
• Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj:
  Monte-Carlo approach for power estimation in sequential circuits. 416-420
  

Formal Methods in Synthesis and Verification

• Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
  Hybrid symbolic-explicit techniques for the graph coloring problem. 422-426
  
• Dirk Eisenbiegler, Ramayya Kumar, Christian Blumenröhr:
  A constructive approach towards correctness of synthesis-application within retiming. 427-431
  
• Stefan Hendricx, Luc J. M. Claesen:
  A symbolic core approach to the formal verification of integrated mixed-mode applications. 432-436
  

Concurrent Checking

• Cristiana Bolchini, Fabio Salice, Donatella Sciuto:
  A novel methodology for designing TSC networks based on the parity bit code. 440-444
  
• Michele Favalli, Cecilia Metra:
  Testing scheme for IC's clocks. 445-449
  
• Antonis M. Paschalis, Nikolaos Gaitanis, Dimitris Gizopoulos, Panagiotis Kostarakis:
  A totally self-checking 1-out-of-3 code error indicator. 450-454
  

New Ideas in Scheduling

• Sriram Govindarajan, Ranga Vemuri:
  Cone-based clustering heuristic for list-scheduling algorithms. 456-462
  
• Dirk Herrmann, Rolf Ernst:
  Register synthesis for speculative computation. 463-467
  
• Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jef L. van Meerbergen:
  Multidimensional periodic scheduling: a solution approach. 468-474
  

System Level Design Representation and Transformation

• Filip Thoen, J. Van Der Steen, Gjalt G. de Jong, Gert Goossens, Hugo De Man:
  Multi-thread graph: a system model for real-time embedded software synthesis. 476-481
  
• Thorsten Grötker, R. Schoenen, Heinrich Meyr:
  PCC: a modeling technique for mixed control/data flow systems. 482-486
  
• Frank Vahid:
  Procedure cloning: a transformation for improved system-level functional partitioning. 487-492
  

Diagnosis and Test Generation

• Sridhar Narayanan, R. Srinivasan, R. P. Kunda, Marc E. Levitt, Saied Bozorgui-Nesbat:
  A fault diagnosis methodology for the UltraSPARC^TM-I microprocessor. 494-500
  
• José T. de Sousa, Peter Y. K. Cheung:
  Improved diagnosis of realistic interconnect shorts. 501-505
  
• Irith Pomeranz, Sudhakar M. Reddy:
  On improving genetic optimization based test generation. 506-511
  

Logic Synthesis for Low Power

• Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
  Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. 514-520
  
• Prasoon Surti, Liang-Fang Chao, Akhilesh Tyagi:
  Low power FSM design using Huffman-style encoding. 521-525
  
• Hoon Choi, Seung Ho Hwang:
  Improving the accuracy of support-set finding method for power estimation of combinational circuits. 526-530
  

System Design Methodologies

• I. Gibson, C. Amies:
  Practical concurrent ASIC and system design and verification. 532-536
  
• C. Schneider:
  A methodology for hardware architecture trade-off at different levels of abstraction. 537-541
  
• Patrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens:
  Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications. 542-546
  

Testability at Different Abstraction Levels

• Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker:
  Testability of 2-level AND/EXOR circuits. 548-553
  
• Irith Pomeranz, Sudhakar M. Reddy:
  On the use of reset to increase the testability of interconnected finite-state machines. 554-559
  
• Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Raimund Ubar:
  A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs. 560-565
  

Hardware and Software Tools for Analog and Mixed-Signal Test

• Michel Renovell, Florence Azaïs, Yves Bertrand:
  On-chip analog output response compaction. 568-572
  
• Thomas Olbrich, Ian A. Grout, Y. E. Aimine, Andrew M. D. Richardson, J. Contensou:
  A new quality estimation methodology for mixed-signal and analogue ICs. 573-580
  
• V. Kaal, Hans G. Kerkhoff:
  Compact structural test generation for analog macros. 581-587
  

Power Estimation and Modeling

• Jim E. Crenshaw, Majid Sarrafzadeh:
  Accurate high level datapath power estimation. 590-596
  
• Salvador Manich, Joan Figueras:
  Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model. 597-602
  
• S. Turgis, Jean Michel Daga, J. M. Portal, Daniel Auvergne:
  Internal power modelling and minimization in CMOS inverters. 603-608
  

Posters

• Julio Faura, C. Horton, B. Krah, Joan Cabestany, M. A. Aguirre, Josep Maria Insenser:
  A new field programmable system-on-a-chip for mixed signal integration. 610
  
• Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess:
  PROPHID: a data-driven multi-processor architecture for high-performance DSP. 611
  
• Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerraya:
  ReCode: the design and re-design of the instruction codes for embedded instruction-set processors. 612
  
• T. Rowekamp, L. Peters:
  A real-time smart sensor system for visual motion estimation. 613
  
• J. Gonzalez-Torres, P. A. Mateos, J. M. Hernandez:
  Full custom chip set for high speed serial communications up to 2.48 Gbit/s. 614
  
• M. R. Karthikeyan, Soumitra Kumar Nandy:
  An asynchronous architecture for digital signal processors. 615
  
• Hassan Ihs, Christian Dufaza:
  Test synthesis for DC test of switched-capacitors circuits. 616
  
• Vladimir Székely, A. Pahi, András Poppe, Márta Rencz, A. Csendes:
  SISSSI-A tool for dynamic electro-thermal simulation of analog VLSI cells. 617
  
• Marina Santo Zarnik, Franc Novak, Srecko Macek:
  Design of oscillation-based test structures for active RC filters. 618
  
• Renate Beckmann, Jürgen Herrmann:
  Using constraint logic programming in memory synthesis for general purpose computers. 619
  
• Igor Ozimek, R. Verlic, Jurij F. Tasic:
  Optimal scheduling for fast systolic array implementations. 620
  
• Anne Mignotte, Olivier Peyran:
  Scheduling using mixed arithmetic: an ILP formulation. 621
  
• Jeffrey Walrath, Ranga Vemuri, W. Bradley:
  Performance verification using partial evaluation and interval analysis. 622
  
• A. Ursu, G. Gruita, S. Zaporojan:
  Design and verification of the sequential systems automata using temporal logic specifications. 623
  
• Markus Wolf, Ulrich Kleine:
  Application independent module generation in analog layouts. 624
  
• Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
  A scheme for multiple on-chip signature checking for embedded SRAMs. 625
  
• Yoshinobu Higami, Kozo Kinoshita:
  Design of partially parallel scan chain. 626
  
• A. J. van de Goor, Georgi Gaydadjiev, Vyacheslav N. Yarmolik, V. G. Mikitjuk:
  March LA: a test for linked memory faults. 627
  
• Ronald D. Blanton, John P. Hayes:
  The input pattern fault model and its application. 628
  
• M. Svajda, B. Straka, Hans A. R. Manhaeve:
  A monolithic off-chip IDDQ monitor. 629
  
• Adam Kristof:
  Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections. 630