DATE 1999: Munich, Germany

@proceedings{DBLP:conf/date/1999,
  title     = {1999 Design, Automation and Test in Europe (DATE '99), 9-12 March
               1999, Munich, Germany},
  booktitle = {DATE},
  publisher = {IEEE Computer Society},
  year      = {1999},
  isbn      = {0-7695-0078-1},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Embedded System Design - The European Technology Driver

• Jouko Junkkari:
  Higher Product Complexity and Shorter Development Time - Continuous Challenge to Design and Test Environment. 2-3
  
• Peter Thoma:
  Automotive Electronics - A Challenge For Systems Engineering. 4
  
• T. W. Williams:
  Testing in Nanometer Technologies. 5-
  

Verification of Sequential Circuits

• Gianpiero Cabodi, Paolo Camurati, Claudio Passerone, Stefano Quer:
  Computing Timed Transition Relations for Sequential Cycle-Based Simulation. 8-12
  
• Youpyo Hong, Peter A. Beerel:
  Symbolic Reachability Analysis of Large Finite State Machines Using Don't Cares. 13-
  

Architectural Issues in Low Power Design

• Enoch Hwang, Frank Vahid, Yu-Chin Hsu:
  FSMD Functional Partitioning for Low Power. 22-27
  
• Gerd Jochens, Lars Kruse, Eike Schmidt, Wolfgang Nebel:
  A New Parameterizable Power Macro-Model for Datapath Components. 29-
  

Design Reuse Repository and IP Architecture

• Annette Reutter, Wolfgang Rosenstiel:
  An Efficient Reuse System for Digital Circuit Design. 38-43
  
• Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Jiro Naganuma, Takeshi Ogura:
  An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture. 44-
  

High Level Verification

• Stefan Höreth, Rolf Drechsler:
  Formal Verification of Word-Level Specifications. 52-57
  
• Hans Eveking, Holger Hinrichsen, Gerd Ritter:
  Automatic Verification of Scheduling Results in High-Level Synthesis. 59-64
  
• Michaela Huhn, Klaus Schneider, Thomas Kropf, George Logothetis:
  Verifying Imprecisely Working Arithmetic Circuits. 65-
  

System-Level Power Optimization

• Massoud Pedram, Qing Wu:
  Battery-Powered Digital CMOS Design. 72-76
  
• Eui-Young Chung, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli:
  Dynamic Power Management for non-stationary service requests. 77-81
  
• Rajeev Murgai, Masahiro Fujita:
  On Reducing Transitions Through Data Modifications. 82-
  

Reconfigurability and Other Issues in Embedded System Design

• Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh, Román Hermida, Milagros Fernández:
  Kernel Scheduling in Reconfigurable Computing. 90-96
  
• Bharat P. Dav:
  CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems. 97-104
  
• Rainer Leupers:
  Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors. 105-
  

Embedded Core Test Approaches

• Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas:
  Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. 112-116
  
• Antonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian:
  An Effective BIST Architecture for Fast Multiplier Cores. 117-121
  
• Issam Alzaher-Noufal, Michael Nicolaidis:
  A CAD Framework for Generating Self-Checking 1 Multipliers Based on Residue Codes. 122-
  

Use of Combinational Verification

• Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell:
  An Efficient Filter-Based Approach for Combinational Verification. 132-137
  
• Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton:
  Using Combinational Verification for Sequential Circuits. 138-144
  
• João P. Marques Silva, Thomas Glass:
  Combinational Equivalence Checking Using Satisfiability and Recursive Learning. 145-149
  
• Stefan Hendricx, Luc J. M. Claesen:
  Formally Verified Redundancy Removal. 150-
  

Gate Level Power Estimation and Optimization

• Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu:
  Logic Transformation for Low Power Synthesis. 158-162
  
• Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
  Glitch Power Minimization by Gate Freezing. 163-167
  
• Winfried Nöth, Reiner Kolla:
  Spanning Tree-based State Encoding for Low Power Dissipation. 168-174
  
• Michael S. Hsiao:
  Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits. 175-
  

Fault Diagnosis Techniques for Analogue Circuits

• Érika F. Cota, Luigi Carro, Marcelo Lubaszewski:
  A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester. 184-188
  
• Alfred V. Gomes, Abhijit Chatterjee:
  Minimal Length Diagnostic Tests for Analog Circuits using Test History. 189-194
  
• Sasikumar Cherubal, Abhijit Chatterjee:
  Parametric Fault Diagnosis for Analog Systems Using Functional Mapping. 195-
  

Resource Sharing in Architectural Synthesis

• Meenakshi Kaul, Ranga Vemuri:
  Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs. 202-209
  
• Christoph Jäschke, Rainer Laur, Friedrich Beckmann:
  Time Constrained Modulo Scheduling with Global Resource Sharing. 210-216
  
• James Smith, Giovanni De Micheli:
  Polynomial Methods for Allocating Complex Components. 217-222
  
• Nazanin Mansouri, Ranga Vemuri:
  Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs. 223-
  

Mixed Signal Characterization and Test

• A. Lechner, J. Ferguson, Andrew Richardson, B. Hermes:
  A Digital Partial Built-In Self-Test for a High Performance Automatic Gain Control Circuit . 232-238
  
• Laurent Latorre, Yves Bertrand, P. Hazard, F. Pressecq, Pascal Nouet:
  Design, Characterization & Modelling of a CMOS Magnetic Field Sensor. 239-243
  
• Zheng Rong Yang, Mark Zwolinski:
  Fast, Robust DC and Transient Fault Simulation for Nonlinear Analog Circuits. 244-248
  
• Franc Novak, Bojan Hvala, Sandi Klavzar:
  On Analog Signature Analysis. 249-
  

System Design Methodologies: Modelling, Analysis, Refinement and Synthesis

• Axel Jantsch, Shashi Kumar, Ahmed Hemani:
  The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems. 256-262
  
• Robert P. Dick, Niraj K. Jha:
  MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis. 263-270
  
• Radim Cmar, Luc Rijnders, Patrick Schaumont, Serge Vernalde, Ivo Bolsens:
  A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement. 271-
  

High Level Test Synthesis

• Joan Carletta, Mehrdad Nourani, Christos A. Papachristou:
  Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs. 278-282
  
• Yiorgos Makris, Alex Orailoglu:
  Channel-Based Behavioral Test Synthesis for Improved Module Reachability. 283-288
  
• Nicola Nicolici, Bashir M. Al-Hashimi:
  Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths. 289-
  

High-Level System Simulation

• Katsuyuki Ochiai, Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura:
  High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit. 303-308
  
• Bassam Tabbara, Marco Sgroi, Alberto L. Sangiovanni-Vincentelli, Enrica Filippi, Luciano Lavagno:
  Fast Hardware-Software Co-simulation Using VHDL Models. 309-
  

Analogue Circuit Sizing and Synthesis

• Chris J. M. Verhoeven, Arie van Staveren:
  Systematic Biasing of Negative Feedback Amplifiers. 318-322
  
• Robert Schwencker, Josef Eckmueller, Helmut E. Graeb, Kurt Antreich:
  Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints. 323-327
  
• Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri:
  Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis. 328-
  

VHDL-AMS and HDL Interoperability

• Alex Doboli, Ranga Vemuri:
  A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems. 338-345
  
• Peter T. Breuer, Natividad Martínez Madrid, Jonathan P. Bowen, Robert B. France, Maria M. Larrondo-Petrie, Carlos Delgado Kloos:
  Reasoning about VHDL and VHDL-AMS using Denotational Semantics. 346-352
  
• Hisashi Sasaki:
  A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine. 353-
  

Transistor Level Test

• Bernard Antaki, Yvon Savaria, Nanhan Xiong, Saman Adham:
  Design For Testability Method for CML Digital Circuits. 360-367
  
• Michele Favalli, Cecilia Metra:
  On the Design of Self-Checking Functional Units Based on Shannon Circuits. 368-375
  
• Dirk Niggemeyer, M. Rüffer:
  Parametric Built-In Self-Test of VLSI Systems. 376-
  

Hot Topic - Hardware Synthesis from C/C++ Models

• Giovanni De Micheli:
  Hardware Synthesis from C/C++ Models. 382-383
  
• Guido Arnout:
  C for System Level Design. 384-386
  
• Abhijit Ghosh, Joachim Kunkel, Stan Y. Liao:
  Hardware Synthesis from C/C++. 387-389
  
• Kazutoshi Wakabayashi:
  C-based Synthesis Experiences with a Behavior Synthesizer, "Cyber". 390-
  

Analogue Modelling and Simulation

• Joao Paulo Costa, L. Miguel Silveira, Mike Chou:
  Efficient Techniques for Accurate Extraction and Modeling of Substrate Coupling in Mixed-Signal IC's. 396-400
  
• Erik Lauwers, Georges G. E. Gielen:
  A Power Estimation Model for High-Speed CMOS A/D Converters. 401-405
  
• Adrián Núñez-Aldana, Ranga Vemuri:
  An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis. 406-411
  
• Oscar Guerra, J. D. Rodríguez-García, Elisenda Roca, Francisco V. Fernández, Ángel Rodríguez-Vázquez:
  An Accurate Error Control Mechanism for Simplification Before Generation Algorihms. 412-
  

Hot Topic - Chip Package Co-Design

• Peter Feldmann, Sharad Kapur, David E. Long:
  Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics. 418-417
  
• Gerhard Tröster:
  Potentials of Chip-Package Co-Design for High-Speed Digital Applications. 423-422
  
• Piet Wambacq, Stéphane Donnay, Hocine Ziad, Marc Engels, Hugo De Man, Ivo Bolsens:
  A Single-Package Solution for Wireless Transceivers. 425-
  

Panel: Scaling Towards Nanometer Technologies: Design for Test Challenges

• Michael Nicolaidis, Yervant Zorian:
  Scaling Deeper to Submicron: On-Line Testing to the Rescue. 432-
  

Functional Verification

• Laurent Fournier, Yaron Arbetman, Moshe Levinger:
  Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator-Application to the x86 Microprocessors Family. 434-441
  
• Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto:
  Symbolic Functional Vector Generation for VHDL Specifications. 442-
  

Bit-Level Logic and Analogue Simulation

• Xiang-Dong Tan, C.-J. Richard Shi:
  Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams. 448-453
  
• Raimund Ubar, Jaan Raik, Adam Morawiec:
  Cycle-based Simulation with Decision Diagrams. 454-458
  
• Markus Bühler, Matthias Papesch, K. Kapp, Utz G. Baitinger:
  Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach. 459-
  

Partial and Boundary Scan Test

• Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
  Full Scan Fault Coverage With Partial Scan. 468-472
  
• Jongchul Shin, Hyunjin Kim, Sungho Kang:
  At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks. 473-
  

New Languages for System Specification and Design

• Jianwen Zhu, Daniel Gajski:
  OpenJ: An Extensible System Level Design Language. 480-484
  
• Ashok Halambi, Peter Grun, Vijay Ganesh, Asheesh Khare, Nikil D. Dutt, Alexandru Nicolau:
  EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability. 485-490
  
• Martin Radetzki, Ansgar Stammermann, Wolfram Putzke-Röming, Wolfgang Nebel:
  Data Type Analysis for Hardware Synthesis from Object-Oriented Models. 491-
  

Circuit Analysis and Design

• Heiko Holzheuer:
  How to use Knowledge in an Analysis Process. 498-502
  
• Lluis Ribas, Jordi Carrabina:
  Digital MOS Circuit Partitioning with Symbolic Modeling. 503-508
  
• Juan A. Montiel-Nelson, Saeid Nooshabadi, V. de Armas, Roberto Sarmiento, Antonio Núñez:
  High Speed GaAs Subsystem Design using Feed Through Logic. 509-
  

Logic Synthesis

• Enrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno:
  Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. 516-520
  
• Manuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas:
  An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length. 521-525
  
• Luís Guerra e Silva, Luis Miguel Silveira, João P. Marques Silva:
  Algorithms for Solving Boolean Satisfiability in Combinational Circuits. 526-530
  
• Leon Stok, Andrew J. Sullivan, Mahesh A. Iyer:
  Wavefront Technology Mapping. 531-
  

IDDX Testing and Defect Modelling

• Viera Stopjaková, Hans A. R. Manhaeve, M. Sidiropulos:
  On-Chip Transient Current Monitor for Testing of Low Voltage CMOS IC. 538-542
  
• Josep Rius, Joan Figueras:
  Exploring the Combination of IDDQ and iDDt Testing: Energy Testing. 543-548
  
• Marcelino B. Santos, João Paulo Teixeira:
  Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL. 549-
  

HW/SW Interface Synthesis and Partitioning

• Steven Vercauteren, Jan van der Steen, Diederik Verkest:
  Combining Software Synthesis and Hardware/Software Interface Generation to Meet Hard Real-Time Constraints. 556-561
  
• Mattias O'Nils, Axel Jantsch:
  Operating System Sensitive Device Driver Synthesis from Implementation Independent Protocol Specification. 562-567
  
• Jui-Ming Chang, Massoud Pedram:
  Codex-dp: Co-design of Communicating Systems Using Dynamic Programming. 568-
  

Physical Design Issues

• A. Toulouse, David Bernard, Christian Landrault, Pascal Nouet:
  Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts. 576-580
  
• Sudip Nag, Kamal Chaudhary:
  Post-Placement Residual-Overlap Removal with Minimal Movement. 581-586
  
• Helena Krupnova, Gabriele Saucier:
  Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs. 587-
  

Reliability and Symmetry in Architectural Synthesis

• Samuel Norman Hamilton, Alex Orailoglu, Andre Hertwig:
  Self Recovering Controller and Datapath Codesign. 596-601
  
• C. A. J. van Eijk, E. T. A. F. Jacobs, Bart Mesman, Adwin H. Timmer:
  Identification and Exploitation of Symmetries in DSP Algorithms. 602-608
  
• Luiz C. V. dos Santos, Jochen A. G. Jess:
  Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation. 609-
  

Panel - Single Chip or Hybrid System Integration?

• Ivo Bolsens, Wojtek Maly, Ludo Deferm, Jo Borel, Harry J. M. Veendrick:
  Single Chip or Hybrid System Integration. 616-
  

Testing Regular Structures and Delay Faults

• Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian:
  Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. 618-622
  
• A. J. van de Goor, J. de Neef:
  Industrial Evaluation of DRAM Tests. 623-630
  
• Spyros Tragoudas, Maria K. Michael:
  ATPG Tools for Delay Faults at the Functional Level. 631-
  

Retiming

• Priyank Kalla, Maciej J. Ciesielski:
  Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence. 638-642
  
• Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman:
  Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. 643-649
  
• Klaus Eckl, Christian Legl:
  Retiming Sequential Circuits with Multiple Register Classes. 650-
  

Modelling of Interconnects

• Lun Ye, Foong-Charn Chang, Peter Feldmann, Rakesh Chadha, Nagaraj Ns, Frank Cano:
  Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs. 658-663
  
• Janet Meiling Wang, Qingjian Yu, Ernest S. Kuh:
  Coupled Noise Estimation for Distributed RC Interconnect Model. 664-668
  
• Bernard N. Sheehan:
  Projective Convolution: RLC Model-Order Reduction Using the Impulse Response. 669-
  

Design Reuse Methodologies for Virtual Components and IP

• Margarida F. Jacome, Helvio P. Peixoto, Ander Royo, Juan Carlos López:
  The Design Space Layer: Supporting Early Design Space Exploration for Core-Based Designs. 676-683
  
• Marcello Dalpasso, Alessandro Bogliolo, Luca Benini:
  Specification and Validation of Distributed IP-Based Designs with JavaCAD. 684-688
  
• Cristina Barna, Wolfgang Rosenstiel:
  Object-Oriented Reuse Methodology for VHDL. 689-
  

Embedded Tutorial - Multilanguage System Design

• Ahmed Amine Jerraya, Rolf Ernst:
  Multi-Language System Design. 696-
  

RAM BIST

• Sybille Hellebrand, Hans-Joachim Wunderlich, Vyacheslav N. Yarmolik:
  Symmetric Transparent BIST for RAMs. 702-707
  
• Kamran Zarrineh, Shambhu J. Upadhyaya:
  On Programmable Memory Built-In Self Test Architectures. 708-713
  
• Kanad Chakraborty, Anurag Gupta, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder:
  A Physical Design Tool for Built-in Self-Repairable Static RAMs. 714-
  

Panel - Java, VHDL-AMS, Ada or C for System Level Specifications?

• Java, VHDL-AMS, ADA or C for System Level Specifications? 720
  
• Eduard Moser, Wolfgang Nebel:
  Case Study: System Model of Crane and Embedded Control. 721-
  

Hot Topic - IP and Reuse

• Jean-François Agaësse, Bernard Laurent:
  Virtual Components Application and Customization. 726-727
  
• Jürgen Haase:
  Design Methodology for IP Providers. 728-
  
• Ralf Seepold:
  Reuse of IP and virtual components.
  

Special Session-Large European Programs in Microelectronic System and Circuit Design

• Patrick Dewilde:
  Large European Programs in Microelectronic System and Circuit Design. 734-
  

Sequential Circuit Test Generation

• Jaan Raik, Raimund Ubar:
  Sequential Circuit Test Generation Using Decision Diagram Models. 736-740
  
• M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor:
  Illegal State Space Identification for Sequential Circuit Test Generation. 741-746
  
• Yanti Santoso, Matthew C. Merten, Elizabeth M. Rudnick, Miron Abramovici:
  FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy. 747-
  

Posters

• Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
  Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms. 754-755
  
• Karsten Strehl, Lothar Thiele:
  Interval Diagram Techniques for Symbolic Model Checking of Petri Nets. 756-757
  
• Mitchell A. Thornton, J. P. Williams, Rolf Drechsler, Nicole Drechsler:
  Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities. 758-759
  
• Christoph Meinel, Christian Stangier:
  Increasing Efficiency of Symbolic Model Checking by Accelerating Dynamic Variable Reordering. 760-761
  
• William Fornaciari, Donatella Sciuto, Cristina Silvano:
  Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems. 762-763
  
• Karlheinz Weiß, Thorsten Steckstor, Wolfgang Rosenstiel:
  Emulation of a Fast Reactive Embedded System using a Real Time Operating System. 764-765
  
• J. A. Maestro, Daniel Mozos, Román Hermida:
  The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach. 766-767
  
• Josef Fleischmann, Klaus Buchenrieder, Rainer Kress:
  Codesign of Embedded Systems Based on Java and Reconfigurable Hardware Components. 768-769
  
• A. Maamar, G. Russell:
  ADOLT - An ADaptable On - Line Testing Scheme for VLSI Circuits. 770-771
  
• Krzysztof Kuchcinski:
  Integrated Resource Assignment and Scheduling of Task Graphs Using Finite Domain Constraints. 772-773
  
• Christos A. Papachristou, Yusuf Alzazeri:
  A Method of Distributed Controller Design for RTL Circuits. 774-775
  
• Jung Hyun Choi, Sergio Bampi:
  OTA Amplifiers Design on Digital Sea-of-Transistors Array. 776-777
  
• Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami:
  A DAG-Based Design Approach for Reconfigurable VLIW Processors. 778-779
  
• Jue Wu, Gary S. Greenstein, Elizabeth M. Rudnick:
  A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis. 780-781
  
• Olivier Pasquier, Jean Paul Calvez:
  An Object-Based Executable Model for Simulation of Real-Time Hw/Sw Systems. 782-783
  
• Stefan Scherber, Christian Müller-Schloer:
  An Efficient and Flexible Methodology for Modelling and Simulation of Heterogeneous Mechatronic Systems. 784-785
  
• Peter M. Maurer, William J. Schilp:
  Software Bit-Slicing: A Technique for Improving Simulation Performance. 786-787
  
• Françoise Martinolle, Charles Dawson, Debra Corlette, Mike Floyd:
  Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUI. 788-789
  
• Jerzy Dabrowski, Andrzej Pulka:
  Experiences with Modeling of Analog and Mixed A/D Systems Based on PWL Technique. 790-791
  
• Iyad Rayane, Jaime Velasco-Medina, Michael Nicolaidis:
  A One-Bit-Signature BIST for Embedded Operational Amplifiers in Mixed-Signal Circuits Based on the Slew-Rate Detection. 792-