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34. DAC 1997: Anaheim, California, USA

Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997. ACM Press, 1997, ISBN 0-89791-920-3

Panel: An Executive View of EDA Industry

Sequential Synthesis

Interconnect Modeling

Novel Techniques for Software Scheduling

Embedded Tutorial: Tools and Methodologies for Low Power Design

Panel: Low-Power Design Tools - Where Is the Impact?

Simulation Techniques for Microprocessors

Combinational Logic Synthesis

Interconnect Parasitic Extraction

Advances in Timing Analysis for Embedded Software

Applications of Formal Verification

System-Level Exploration and Refinement

Binary Decision Diagrams

Timing Analysis

Tutorial: Code Generation for Core Processors

Panel: Physical Design and Synthesis: Merge or Die!

System-Level Optimization and Verification

Formal Verification

Analog Simulation

Software Synthesis for Embedded Systems

Experiences in System Design and Education at Universities

Standard Cell and Physical Design Methods

Modeling and Transformations in Synthesis

Statistical Power Estimation Techniques

Co-Simulation

Panel: Challenges in Worldwide IP Reuse with Embedded Tutorial: Applying VSIA Standards to System on Chip Design

Emerging Technologies and Architectures for Low Power

High Level Synthesis for Low Power

Module Generation

BIST and DFT

Panel: Hardware/Software Co-Verification

DSP & Telecommunication System Design

Embedded Tutorial: High-Level Power Modeling, Estimation, and Optimization

Advances in Partitioning

Processor Test techniques

Panel: The Next Generation HDL

Design Processes and Frameworks

Probabilistic Models of Input Data for Efficient Power Estimation

Hot Topics in Routing

Test Generation and Fault Simulation

Panel: The Road Ahead in CPLD & FPGA Design Methodology

Deep Submicron Modeling and Analysis

Technology-Dependent Optimization for Performance and Power

CAD Issues for Micro-Electro-Mechanical Systems

Hardware/Software Partitioning

Embedded Tutorial: Chip Parasitic Extraction and Signal Integrity Verification

Panel: Noise and Signal Integrity in Deep Submicron Design

Designing High Performance and Low Power Microprocessors Using Full Custom Techniques

Formal Verification techniques

Placement Techniques

Panel: The EDA Startup Experience: Financing the Venture

Heterogeneous System Analysis

Copyright © Mon Nov 2 20:27:54 2009 by Michael Ley (ley@uni-trier.de)