28. DAC 1991: San Francisco, California, USA

Application of Mixed Integer Linear Programming to High-Level Synthesis

• Catherine H. Gebotys, Mohamed I. Elmasry:
  Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis. 2-7
  
• Shiv Prakash, Alice C. Parker:
  Synthesis of Application-Specific Multiprocessor Architectures. 8-13
  
• Louis J. Hafer:
  Constraint improvements for MILP-based hardware synthesis. 14-19
  

Circuit and Timing Simulation

• Yung-Ho Shih, Sung-Mo Kang:
  ILLIADS: A New Fast MOS Timing Simulator Using Direct Equation-Solving Approach. 20-25
  
• Alexander D. Stein, Tuyen V. Nguyen, Binay J. George, Ronald A. Rohrer:
  ADAPTS: A Digital Transient Simulation Strategy for Integrated Circuits. 26-31
  
• Chandramouli Visweswariah, Ronald A. Rohrer:
  Efficient Simulation of Bipolar Digital ICs. 32-37
  

Panel

• Harvey Jones: Global Stratgies for Electronic Design (Panel Abstract). 38

Multi-Layer Area Routing

• Wayne Wei-Ming Dai, Tal Dayan, David Staepelaere:
  Topological Routing in SURF: Generating a Rubber-Band sketch. 39-44
  
• Wayne Wei-Ming Dai, Raymond Kong, Masao Sato:
  Routability of a Rubber-Band Sketch. 45-48
  
• Deborah C. Wang:
  Novel Routing Schemes for IC Layout, Part I: Two-Layer Channel Routing. 49-53
  
• Manuela Raith, Marc Bartholomeus:
  A New Hypergraph Based Rip-Up and Reroute Strategy. 54-59
  
• Sung-Chuan Fang, Kuo-En Chang, Wu-Shiung Feng, Sao-Jie Chen:
  Constrained via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Problems. 60-65
  

Synthesis and Delay Testing

• Andrzej Krasniewski:
  Logic Synthesis for Efficient Pseudoexhaustive Testability. 66-72
  
• Weiwei Mao, Michael D. Ciletti:
  Correlation-Reduced Scan-path Design To Improve Delay Fault Coverage. 73-79
  
• Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer:
  Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology. 80-86
  
• Thomas W. Williams, Bill Underwood, M. Ray Mercer:
  The Interdependence Between Delay-Optimization of Synthesized Networks and Testing. 87-92
  

Technology Mapping

• M. Crastes, K. Sakouti, Gabriele Saucier:
  A Technology Mapping Method Based On Perfect And Semi-Perfect Matchings. 93-98
  
• Massoud Pedram, Narasimha B. Bhat:
  Layout Driven Technology Mapping. 99-105
  
• Van Morgan, David Gregory:
  An ECL Logic Synthesis System. 106-111
  
• Ko Yoshikawa, Hiroshi Ichiryu, Hisato Tanishita, Shigenobu Suzuki, Nobuyoshi Nomizu, Akira Kondoh:
  Timing Optimization on Mapped Circuits. 112-117
  

Design Automation in the Soviet Union

• Gennady G. Kazyonnov: Design Automation in the Soviet Union: History and Status (Abstract). 118

Panel

• Andrew Rappaport: Implementing the Vision: Electronic Design in the 1990's (Panel Abstract). 119

Over the Cell Channel Routing

• Min-Siang Lin, Hourng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin:
  Channel Density Reduction by Routing Over The Cells. 120-125
  
• Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh:
  New Algorithm for Over-the-Cell Channel Routing Using Vacant Terminals. 126-131
  
• Richard J. Enbody, Gary Lynn, Kwee Heong Tan:
  Routing the 3-D Chip. 132-137
  

Fault Simulation

• E. Vandris, Gerald E. Sobelman:
  Algorithms for Fast, Memory Efficient Switch-Level Fault Simulation. 138-143
  
• Vijay Pitchumani, Pankaj Mayor, Nimish Radia:
  A System for Fault Diagnosis and Simulation of VHDL Descriptions. 144-150
  
• Yoshihiro Kitamura:
  Sequential Circuit Fault Simulation by Fault Information Tracing Algorithm: FIT. 151-154
  
• Srinivas Patil, Prithviraj Banerjee, Janak H. Patel:
  Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors. 155-159
  
• Pier Luca Montessoro, Silvano Gai:
  Creator: General and Efficient Multilevel Concurrent Fault Simulation. 160-163
  

Sequential Synthesis

• Kwang-Ting Cheng:
  On Removing Redundancy in Sequential Circuits. 164-169
  
• Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  A Framework for Satisfying Input and Output Encoding Constraints. 170-175
  
• Maciej J. Ciesielski, Jia-Jye Shen, Marc Davio:
  A Unified Approach to Input-Output Encoding for FSM State Assignment. 176-181
  
• Martin Geiger, Thomas Müller-Wipperfürth:
  FSM Decomposition Revisited: Algebraic Structure Theory Applied to MCNC Benchmark FSMs. 182-185
  

Panel

• Michael C. McFarland: Intellectual Property (Panel Abstract). 186

Leading-Edge Design Systems

• Dwight D. Hill:
  A CAD System for the Design of Field Programmable Gate Arrays. 187-192
  
• Hidekazu Terai, Fumio Goto, Katsuro Wakai, Tokinori Kozawa, Mitsugu Edagawa, Satoshi Hososaka, Masahiro Hashimoto:
  Basic Concepts of Timing-oriented Design Automation for High-performance Mainframe Computers. 193-198
  
• Charles R. Yount, Daniel P. Siewiorek:
  SIDECAR: Design Support for Reliability. 199-204
  

Improving Simulator Performance

• Wing Yee Au, Daniel Weise, Scott Seligman:
  Automatic Generation of Compiled Simulations through Program Specialization. 205-210
  
• Larry G. Jones:
  Accelerating Switch-Level Simulation by Function Caching. 211-214
  
• Marko P. Chew, Andrzej J. Strojwas:
  Utilizing Logic Information in Multi-Level Timing Simulation. 215-218
  
• Alok Jain, Randal E. Bryant:
  Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators. 219-222
  
• Jack V. Briner Jr., John L. Ellis, Gershon Kedem:
  Breaking the Barrier of Parallel Simulation of Digital Systems. 223-226
  

Synthesis for Programmable Gate Arrays

• Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic:
  Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs. 227-233
  
• Silvia Ercolani, Giovanni De Micheli:
  Technology Mapping for Electrically Programmable Gate Arrays. 234-239
  
• Kevin Karplus:
  Xmap: A Technology Mapper for Table-Lookup Field-Programmable Gate Arrays. 240-243
  
• Kevin Karplus:
  Amap: A Technology Mapper for Selector-Based Field-Programmable Gate Arrays. 244-247
  
• Nam Sung Woo:
  A Heuristic Method for FPGA Technology Mapping Based on the Edge Visibility. 248-251
  

Panel

• Wojciech Maly: What is Design for Manufacturability (DFM)? (Panel Abstract). 252

Layout Systems

• Yasushi Ogawa, Tsutomu Itoh, Yoshio Miki, Tatsuki Ishii, Yasuo Sato, Reiji Toyoshima:
  Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design. 253-258
  
• Christian Masson, Remy Escassut, Denis Barbier, Daniel Winer, Gregory Chevallier:
  Object Oriented Lisp Implementation of the CHEOPS VLSI Floor Planning and Routing System. 259-264
  
• Krzysztof Kozminski:
  Benchmarks for Layout Synthesis - Evolution and Current Status. 265-270
  

Design for Testability and Built In Self Test

• Scott Chiu, Christos A. Papachristou:
  A Design for Testability Scheme with Applications to Data Path Synthesis. 271-277
  
• Tapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin:
  Enhanced Controllability for I_DDQ Test Sets Using Partial Scan. 278-281
  
• Susheel J. Chandra, Tom Ferry, Tushar Gheewala, Kerry Pierce:
  ATPG Based on a Novel Grid-Addressable Latch Element. 282-286
  
• Chien-In Henry Chen:
  Graph Partitioning for Concurrent Test Scheduling in VLSI Circuit. 287-290
  
• David M. Wu, Charles E. Radke:
  Delay Test Effectiveness Evaluation of LSSD-Based VLSI Vogic Circuits. 291-295
  

Synthesis of Asynchronous Circuits

• Kuan-Jen Lin, Chen-Shang Lin:
  Automatic Synthesis of Asynchronous Circuits. 296-301
  
• Luciano Lavagno, Kurt Keutzer, Alberto L. Sangiovanni-Vincentelli:
  Algorithms for Synthesis of Hazard-Free Asynchronous Circuits. 302-308
  
• Maureen Ladd, William P. Birmingham:
  Synthesis of Multiple-Input Change Asynchronous Finite state Machines. 309-314
  

Panel

• A. Richard Newton: Framework Standards: How Important are They? (Panel Abstract). 315

Global Considerations in Routing

• Robert C. Carden IV, Chung-Kuan Cheng:
  A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow Algorithm. 316-321
  
• Andrew B. Kahng, Jason Cong, Gabriel Robins:
  High-Performance Clock Routing Based on Recursive Geometric Aatching. 322-327
  
• Yang Cai, D. F. Wong:
  On Minimizing the Number of L-Shaped Channels. 328-334
  
• Mohankumar Guruswamy, D. F. Wong:
  A General Multi-Layer Area Router. 335-340
  

Test Pattern Generation

• Irith Pomeranz, Sudhakar M. Reddy:
  On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model. 341-346
  
• Stephen Pateras, Janusz Rajski:
  Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits. 347-352
  
• Srimat T. Chakradhar, Vishwani D. Agrawal:
  A Transitive Closure Based Algorithm for Test Generation. 353-358
  
• Srinivas Devadas, Kurt Keutzer, Sharad Malik:
  A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults. 359-365
  

Datapath and Control Synthesis

• David C. Ku, Dave Filo, Giovanni De Micheli:
  Control Optimization Based on Resynchronization of Operations. 366-371
  
• Bernhard Eschermann, Hans-Joachim Wunderlich:
  A Unified Approach for the Synthesis of Self-Testable Finite State Machines. 372-377
  
• Christos A. Papachristou, Scott Chiu, Haidar Harmanani:
  A Data Path Synthesis Method for Self-Testable Designs. 378-384
  
• Vijay Raghavendra, Chidchanok Lursinsap:
  Automated Micro-Roll-back Self-Recovery Synthesis. 385-390
  

Formal Design Verification

• Holger Busch, Gerd Venzl:
  Proof-Aided Design of Verified Hardware. 391-396
  
• Randal E. Bryant, Derek L. Beatty, Carl-Johan H. Seger:
  Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation. 397-402
  
• Jerry R. Burch, Edmund M. Clarke, David E. Long:
  Representing Circuits More Efficiently in Symbolic Model Checking. 403-407
  
• Jerry R. Burch:
  Using BDDs to Verify Multipliers. 408-412
  
• Hiroyuki Ochi, Nagisa Ishiura, Shuzo Yajima:
  Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing. 413-416
  
• Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer:
  Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams. 417-420
  

Partitioning and Placement

• Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
  A General Purpose Multiple Way Partitioning Algorithm. 421-426
  
• Georg Sigl, Konrad Doll, Frank M. Johannes:
  Analytical Placement: A Linear or a Quadratic Objective Function? 427-432
  
• Hidetoshi Onodera, Yo Taniguchi, Keikichi Tamaru:
  Branch-and-Bound Placement for Building Block Layout. 433-439
  

Testability Analysis

• Wen Ching Wu, Chung-Len Lee:
  A Probabilistic Testability Measure for Delay Faults. 440-445
  
• Peter A. Beerel, Teresa H. Y. Meng:
  Testability of Asynchronous Timed Control Circuits with Delay Assumptions. 446-451
  
• Sarma Sastry, Amitava Majumdar:
  A Branching Process Model for Observability Analysis of Combinational Circuits. 452-457
  

Logic Optimization

• Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita:
  A Resynthesis Approach for Network Optimization. 458-463
  
• Johnson Chan Limqueco, Saburo Muroga:
  Logic Optimization of MOS Networks. 464-469
  
• Søren Søe, Kevin Karplus:
  Logic Minimization using Two-column Rectangle Replacement. 470-473
  

Panel

• Gerd Venzl: Are Formal Methods in Design for Real? (Panel Abstract). 474

Module Generators

• King C. Ho, Sarma Sastry:
  Flexible Transistor Matrix (FTM). 475-480
  
• Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu:
  An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. 481-486
  
• Robert L. Maziasz, John P. Hayes:
  Exact Width and Height Minimization of CMOS Cells. 487-493
  

CAD for Analog Cells and ICs

• Scott D. Huss, Ronald S. Gyurcsik:
  Optimal Ordering of Analog Integrated Circuit Tests to Minimize Test Time. 494-499
  
• George Gad-El-Karim, Ronald S. Gyurcsik:
  Generation of Performance Sensitivities for Analog Cell Layout. 500-505
  
• Louis-Oliver Donzelle, Pierre-François Dubois, B. Hennion, J. Parissis, P. Senn:
  A Constraint Based Approach to Automatic Design of Analog Cells. 506-509
  
• Masato Mogaki, Naoki Kato, Naomi Shimada, Yuriko Yamada:
  A Layout Improvement Method Based on Constraint Propagation for Analog LSI's. 510-513
  

Interfacing to High-Level Synthesis: Above and Below

• Kayhan Küçükçakar, Alice C. Parker:
  CHOP: A Constraint-Driven System-Level Partitioner. 514-519
  
• Thomas E. Fuhrman:
  Industrial Extensions to University High Level Synthesis Tools: Making It Work in the Real World. 520-525
  
• Nikil D. Dutt, James R. Kipps:
  Bridging High-Level Synthesis to RTL Technology Libraries. 526-529
  
• Alice C. Parker, Pravil Gupta, Agha Hussain:
  The Effects of Physical Design Characteristics on the Area-Performance Tradeoff Curve. 530-534
  

Critical Path Analysis of Logic Gate Networks

• Li-Ren Liu, David Hung-Chang Du, Hsi-Chuan Chen:
  An Efficient Parallel Critical Path Algorithm. 535-540
  
• Yun-Cheng Ju, Resve A. Saleh:
  Incremental Techniques for the Identification of Statically Sensitizable Critical Paths. 541-546
  
• Hsi-Chuan Chen, David Hung-Chang Du, Li-Ren Liu:
  Critical Path Selection for Performance Optimization. 547-550
  
• Jengwei Pan, Larry L. Biro, Joel Grodstein, William J. Grundmann, Yao-Tsung Yen:
  Timing Verification on a 1.2M-Device Full-Custom CMOS Design. 551-554
  

Timing Modeling of Interconnect

• Curtis L. Ratzlaff, Nanda Gopal, Lawrence T. Pillage:
  RICE: Rapid Interconnect Circuit Evaluator. 555-560
  
• Vivek Raghavan, Ronald A. Rohrer:
  A New Nonlinear Driver Model for Interconnect Analysis. 561-566
  
• Heinz Mattes, Wolfgang Weisenseel, Gerhard Bischof, Reimund Dachauer:
  Propagation Delay Calculation for Interconnection Nets on Printed Circuit Boards by Reflected Waves. 567-572
  

Technology CAD

• Goodwin R. Chin, Walter C. Dietrich Jr., Duane S. Boning, Alexander S. Wong, Andrew R. Neureuther, Robert W. Dutton:
  Linking TCAD to EDA - Benefits and Issues. 573-578
  
• D. M. H. Walker, Chris S. Kellen, Andrzej J. Strojwas:
  A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator. 579-584
  
• Lifeng Wu, Zhilian Yang, Zhiping Yu, Zhijian Li:
  GOALSERVER: A Multiobjective Design Optimization Tool for IC Fabrication Process. 585-590
  

Synthesis of High-Performance Systems

• Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer:
  Data-Path Synthesis Using Path Analysis. 591-596
  
• Stefaan Note, Werner Geurts, Francky Catthoor, Hugo De Man:
  Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications. 597-602
  
• C. Y. Roger Chen, Michael Z. Moricz:
  Datapath Scheduling for Two-Level Pipelining. 603-606
  
• Barry M. Pangrle, Forrest Brewer, Donald Lobo, Andrew Seawright:
  Relevant Issues in High-Level Connectivity Synthesis. 607-610
  

Panel

• Alberto L. Sangiovanni-Vincentelli: Testability Solutions: Who Really Wants Them? (Panel Abstract). 611

Placement for Performance Optimization

• Jacques Benkoski, Andrzej J. Strojwas:
  The Role of Timing Verification in Layout Synthesis. 612-619
  
• Ren-Song Tsay, Jürgen Koehl:
  An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement. 620-625
  
• Wing K. Luk:
  A Fast Physical Constraint Generator for Timing Driven Layout. 626-631
  
• Suphachai Sutanthavibul, Eugene Shragowitz:
  Dynamic Prediction of Critical Paths and Nets for Constructive Timing-Driven Placement. 632-635
  
• Arvind Srinivasan:
  An Algorithm for Performance-Driven Initial Placement of Small-Cell ICs. 636-639
  
• Donald A. Joy, Maciej J. Ciesielski:
  Placement for Clock Period Minimization With Multiple Wave Propagation. 640-643
  

Extending the Functionality of Discrete Simulation

• Farid N. Najm:
  Transition Density, A Stochastic Measure of Activity in Digital Circuits. 644-649
  
• Yutaka Deguchi, Nagisa Ishiura, Shuzo Yajima:
  Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits. 650-655
  
• Tod Amon, Gaetano Borriello:
  OEsim: A Simulator for Timing Behavior. 656-661
  
• Dimitris Doukas, Andrea S. LaPaugh:
  CLOVER: A Timing Constraints Verification System. 662-667
  

Scheduling in High-Level Synthesis I

• Jen-Pin Weng, Alice C. Parker:
  3D Scheduling: High-Level Synthesis with Floorplanning. 668-673
  
• Tai A. Ly, Jack T. Mowchenko:
  Bottom Up Synthesis Based on Fuzzy Schedules. 674-679
  
• In-Cheol Park, Chong-Min Kyung:
  Fast and Near Optimal Scheduling in Automatic Data Path Aynthesis. 680-685
  
• Rajiv Jain, Ashutosh Mujumdar, Alok Sharma, Hueymin Wang:
  Empirical Evaluation of Some High-Level Synthesis Scheduling Heuristics. 686-689
  
• Tod Amon, Gaetano Borriello:
  Sizing Synchronization Queues: A Case Study in Higher Level Synthesis. 690-693
  

Frameworks

• Wayne Allen, Douglas Rosenthal, Kenneth W. Fiduk:
  The MCC CAD Framework Methodology Management System. 694-698
  
• Steve Banks, Catherine Bunting, Russ Edwards, Laura Fleming, Peter Hackett:
  A Configuration Management System in a Data Management Framework. 699-703
  
• Flávio Rech Wagner, Arnaldo Hilário Viegas de Lima:
  Design Version Management in the GARDEN Framework. 704-710
  
• K. Olav ten Bosch, Peter Bingley, Pieter van der Wolf:
  Design Flow Management in the NELSIS CAD Framework. 711-716
  

Geometric Algorithms

• Jerry P. Hwang:
  REX - A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis. 717-722
  
• Matthias C. Utesch:
  A New Approach to Hierarchical Adaptation Using Sequence-Control Based on Cell Interactions. 723-726
  
• Paul de Dood, John Wawrzynek, Erwin Liu, Roberto Suaya:
  A Two-Dimensional Topological Compactor With Octagonal Geometry. 727-731
  
• Andrew J. Harrison:
  VLSI Layout Compaction Using Radix Priority Search Trees. 732-735
  
• Debaprosad Dutt, Chi-Yuan Lo:
  On Minimal Closure Constraint Generation for Symbolic Cell Assembly. 736-739
  

Transmission Line and Interconnect Simulation

• Jaijeet S. Roychowdhury, Donald O. Pederson:
  Efficient Transient Simulation of Lossy Interconnect. 740-745
  
• J. S. Barkatullah, S. Chowdhury:
  A Transmission Line Simulator for GaAs Integrated Circuits. 746-751
  
• Andrew T. Yang, C. H. Chan, Jack T. Yao, R. R. Daniels, J. P. Harrang:
  Modeling and Simulation of High-Frequency Integrated Circuits Based on Scattering Parameters. 752-757
  

Scheduling in High-Level Synthesis II

• Xiaobo Hu, Ronald G. Harber, Steven C. Bass:
  Minimizing the Number of Delay Buffers in the Synchronization of Pipelined Systems. 758-763
  
• Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin:
  Scheduling for Functional Pipelining and Loop Winding. 764-769
  
• Alexandru Nicolau, Roni Potasman:
  Incremental Tree Height Reduction for High Level Synthesis. 770-774
  
• Donald Lobo, Barry M. Pangrle:
  Redundant Operator Creation: A Scheduling Optimization Technique. 775-778
  

Panel

• Jonathan Rose: Will the Field-Programmable Gata Array Replace the Mask-Programmable Gate Array? (Panel Abstract). 779