46. DAC 2009:
USA Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009.
ACM 2009, ISBN 978-1-60558-497-3
Mechanisms for surviving uncertainty:
opportunities and prospects
- Keith A. Bowman, James Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar:
Circuit techniques for dynamic variation tolerance.
- Emre Tuncer, Jordi Cortadella, Luciano Lavagno:
Enabling adaptability through elastic clocks.
- Shidhartha Das, David Blaauw, David Bull, Krisztián Flautner, Rob Aitken:
Addressing design margins through error-tolerant circuits.
Combating non-idealities in static timing analysis
advances in system-level exploration and optimization
- Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon:
Way Stealing: cache-assisted automatic instruction set extensions.
- Zhonglei Wang, Andreas Herkersdorf, Wolfgang Haberl, Martin Wechs:
SysCOLA: a framework for co-development of automotive software and system platform.
- Michael Glaß, Martin Lukasiewycz, Jürgen Teich, Unmesh D. Bordoloi, Samarjit Chakraborty:
Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis.
- Jungseob Lee, Nam Sung Kim:
Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating.
Novel design and verification methodologies
- Thorlindur Thorolfsson, Kiran Gonsalves, Paul D. Franzon:
Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study.
- Yan Pan, Joonho Kong, Serkan Ozdemir, Gokhan Memik, Sung Woo Chung:
Selective wordline voltage boosting for caches to manage yield under process variations.
- Kun Yuan, Katrina Lu, David Z. Pan:
Double patterning lithography friendly detailed routing with redundant via consideration.
- David Abercrombie, Fedor Pikus, Cosmin Cazan:
Use of lithography simulation for the calibration of equation-based design rule checks.
Design and optimization of nanocircuits
Dawn of the 22nm design era - yes we can!
Statistical methods in static timing analysis
- Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He:
Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability.
- Shingo Takahashi, Yuki Yoshida, Shuji Tsukiyama:
A Gaussian mixture model for statistical timing analysis.
- James R. Burnham, Chih-Kong Ken Yang, Haitham A. Hindi:
A stochastic jitter model for analyzing digital timing-recovery circuits.
- Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov:
Statistical ordering of correlated timing quantities and its application for path ranking.
- Ayhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik:
A parametric approach for handling local variation effects in timing analysis.
test and debug of embedded systems
- Karthik Shankar, Roman L. Lysecky:
Non-intrusive dynamic application profiling for multitasked applications.
- Chun-Hung Lai, Fu-Ching Yang, Chung-Fu Kao, Ing-Jer Huang:
A trace-capable instruction cache for cost efficient real-time program trace compression in SoC.
- Thanh Nga Dang, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra:
Generating test programs to cover pipeline interactions.
- Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Alan Peisheng Su:
NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core.
Low-power design and analysis techniques
- Vineeth Veetil, Dennis Sylvester, David Blaauw, Saumil Shah, Steffen Rochel:
Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence.
- Eli Arbel, Cindy Eisner, Oleg Rokhlenko:
Resurrecting infeasible clock-gating functions.
- Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng:
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.
- Cedric Walravens, Yves Vanderperren, Wim Dehaene:
ActivaSC: a highly efficient and non-intrusive extension for activity-based analysis of SystemC models.
Design integrity challenges
- Jin Shi, Yici Cai, Wenting Hou, Liwei Ma, Sheldon X.-D. Tan, Pei-Hsin Ho, Xiaoyi Wang:
GPU friendly fast Poisson solver for structured power grid network analysis.
- Nahi H. Abdul Ghani, Farid N. Najm:
Fast vectorless power grid verification using an approximate inverse technique.
- Görschwin Fey, André Sülflow, Rolf Drechsler:
Computing bounds for fault tolerance using formal techniques.
- Sari Onaissi, Khaled R. Heloue, Farid N. Najm:
Clock skew optimization via wiresizing for timing sign-off covering all process corners.
Verifying an SOC monster:
whose job is it anyway?
- Pradip A. Thaker:
Holistic verification: myth or magic bullet?
- Warren Stapleton, Paul Tobin:
Verification problems in reusing internal design components.
- Dave Whipp:
Exploiting "architecture for verification" to streamline the verification process.
- Eric Chesters:
Role of the verification team throughout the ASIC development life cycle.
optimized embedded software and MPSOCs
Advances in embedded system modeling and optimization
Interconnect optimization for emerging technologies
anyway you want it!
- Michael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer:
Soft connections: addressing the hardware-design modularity problem.
- Andrei Hagiescu, Weng-Fai Wong, David F. Bacon, Rodric M. Rabbah:
A computing origami: folding streams in FPGAs.
- Dmitry Bufistov, Jordi Cortadella, Marc Galceran Oms, Jorge Júlvez, Michael Kishinevsky:
Retiming and recycling for elastic systems with early evaluation.
- Marc Galceran Oms, Jordi Cortadella, Michael Kishinevsky:
Speculation in elastic systems.
blue-sky research or CMOS replacement?
from chip to package
- Chih-Hung Liu, Shih-Yi Yuan, Sy-Yen Kuo, Yao-Hsin Chou:
An O(n log n) path-based obstacle-avoiding algorithm for rectilinear Steiner tree construction.
- Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth:
GRIP: scalable 3D global routing using integer programming.
- Hui Kong, Tan Yan, Martin D. F. Wong:
Automatic bus planner for dense PCBs.
- Tan Yan, Martin D. F. Wong:
A correct network flow model for escape routing.
- Jia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang:
Flip-chip routing with unified area-I/O pad assignments for package-board co-design.
Speed path identification and silicon debug
Analog/RF simulation and statistical modeling
Recent advances in timing,
ECO and logic optimization
- Mihir R. Choudhury, Kartik Mohanram:
Timing-driven optimization using lookahead logic circuits.
- Kuo-Hua Wang, Chung-Ming Chan, Jung-Chang Liu:
Simulation and SAT-based Boolean matching for large Boolean networks.
- Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang:
New spare cell design for IR drop minimization in Engineering Change Order.
- Iris Hui-Ru Jiang, Hua-Yu Chang, Liang-Gi Chang, Huang-Bi Hung:
Matching-based minimum-cost spare cell selection for design changes.
- Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo:
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers.
Computation in the post-Turing era
Advances in physical synthesis
Jumping the high-level verification hurdle
Novel techniques to minimize circuit failure
- Jian Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi:
SRAM parametric failure analysis.
- Weiguang Sheng, Liyi Xiao, Zhigang Mao:
Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm.
- Smita Krishnaswamy, Igor L. Markov, John P. Hayes:
Improving testability and soft-error resilience through retiming.
- Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan Yang, Xuan Zeng:
Statistical reliability analysis under process variation and aging effects.
- Geoffrey Ying, Andreas Kuehlmann, Kenneth S. Kundert, Georges G. E. Gielen, Eric Grimme, Martin O'Leary, Sandeep Tare, Warren Wong:
Guess, solder, measure, repeat: how do I get my mixed-signal chip right?
Multicore computing and EDA
Layout-based variability modeling and optimization
Advances in core verification techniques
Future interconnect technologies:
how do on-chip networks evolve?
- Zheng Li, Dan Fay, Alan Mickelson, Li Shang, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun:
Spectrum: a hybrid nanophotonic-electric on-chip network.
- Sudeep Pasricha:
Exploring serial vertical interconnects for 3D ICs.
- Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Yi-Chao Chan, Tien-Fu Chen, Chao-Ching Wang, Jinn-Shyan Wang:
No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips.
Robust analog system design
wild and crazy ideas
- Atanu Chattopadhyay, Zeljko Zilic:
Serial reconfigurable mismatch-tolerant clock distribution.
- José Luis Ayala, David Atienza, Philip Brisk:
Thermal-aware data flow analysis.
- Mustafa Altun, Marc D. Riedel, Claudia Neuhauser:
Nanoscale digital computation through percolation.
- Bo Marr, Arindam Basu, Stephen Brink, Paul E. Hasler:
A learning digital computer.
- Shimeng Huang, Joseph Oresko, Yuwen Sun, Allen C. Cheng:
Programmable neural processing on a smartdust.
- Andrew DeOrio, Valeria Bertacco:
Human computing for EDA.
- Andreas Raabe, Rastislav Bodík:
Synthesizing hardware from sketches.
- Pai H. Chou:
Endosymbiotic computing: enabling surrogate GUI and cyber-physical connectivity.
The tool shows that my design is wrong,
but where is the bug?
- Masahiro Fujita, Yoshihisa Kojima, Amir Masoud Gharehbaghi:
Debugging from high level down to gate level.
- Andreas G. Veneris, Sean Safarpour:
The day Sherlock Holmes decided to do EDA.
- Valeria Bertacco:
Debugging strategies for mere mortals.
- Gila Kamhi, Alexander Novakovsky, Andreas Tiemeyer, Adriana Wolffberg:
MAGENTA: transaction-based statistical micro-architectural root-cause analysis.
- Michael Siegel, Adriana Maggiore, Christian Pichler:
Untwist your brain: efficient debugging and diagnosis of complex assertions.
- Rajeev K. Ranjan, Claudionor Coelho, Sebastian Skalberg:
Beyond verification: leveraging formal for debugging.
Embedded system design for low-power
characterization and trusted design
- Ryan Helinski, Dhruva Acharyya, Jim Plusquellic:
A physical unclonable function defined using power distribution system equivalent resistance variations.
- Daniel Y. Deng, Andrew H. Chan, G. Edward Suh:
Hardware authentication leveraging performance limits in detailed simulations and emulations.
- Miodrag Potkonjak, Ani Nahapetian, Michael Nelson, Tammara Massey:
Hardware Trojan horse detection using gate-level characterization.
- Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, Russ Joseph:
Process variation characterization of chip-level multiprocessors.
- Junjun Gu, Gang Qu, Qiang Zhou:
Information hiding for trusted system design.
Targeted test and diagnosis
Challenges of memory-aware design for embedded systems
Parasitic extraction in the face of process variability
allocation and reliability
- Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha:
Throughput optimal task allocation under thermal constraints for multi-core processors.
- Shaobo Liu, Qing Wu, Qinru Qiu:
An adaptive scheduling and voltage/frequency selection algorithm for real-time energy harvesting systems.
- Vijay Janapa Reddi, Meeta Sharma Gupta, Michael D. Smith, Gu-Yeon Wei, David M. Brooks, Simone Campanoni:
Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack.
- Hochang Jang, Taewhan Kim:
Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization.
Network-on-chip advances for power,
reliability and the memory bottleneck
- Wooyoung Jang, David Z. Pan:
An SDRAM-aware router for Networks-on-Chip.
- Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi:
Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency.
- David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David Blaauw, Dennis Sylvester:
Vicis: a reliable network for unreliable silicon.
- Siddharth Garg, Diana Marculescu, Radu Marculescu, Ümit Y. Ogras:
Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective.
- Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
NoC topology synthesis for supporting shutdown of voltage islands in SoCs.
Leveraging parallelism in FPGAs and multicore systems
Space and time management in embedded applications
- Mahmut T. Kandemir, Ozcan Ozturk, Sai Prashanth Muralidhara:
Dynamic thread and data mapping for NoC based CMPs.
- Yuan-Hao Chang, Tei-Wei Kuo:
A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systems.
- Soheil Samii, Petru Eles, Zebo Peng, Anton Cervin:
Quality-driven synthesis of embedded multi-mode control systems.
- Lei Ju, Bach Khoa Huynh, Samarjit Chakraborty, Abhik Roychoudhury:
Context-sensitive timing analysis of Esterel programs.
- Haibo Zeng, Wei Zheng, Marco Di Natale, Arkadeb Ghosal, Paolo Giusto, Alberto L. Sangiovanni-Vincentelli:
Scheduling the FlexRay bus using optimization techniques.
Technologies for green data centers
How to improve your memory
Scheduling in time and space
Heuristic approaches to hardware optimization
Model order reduction techniques and applications
Copyright © Mon Nov 2 20:27:58 2009
by Michael Ley (firstname.lastname@example.org)
- Jorge Fernandez Villena, Luis Miguel Silveira:
ARMS - automatic residue-minimization based sampling for multi-point modeling techniques.
- N. Wong:
An efficient passivity test for descriptor systems via canonical projector techniques.
- Zhenhai Zhu:
A parameterized mask model for lithography simulation.