42. DAC 2005:
USA William H. Joyner Jr., Grant Martin, Andrew B. Kahng (Eds.):
Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005.
ACM 2005, ISBN 1-59593-058-2
Microarchitecture-level power analysis and optimization techniques
Leakage analysis and optimization
Statistical timing analysis
- Hongliang Chang, Vladimir Zolotov, Sambasivan Narayan, Chandu Visweswariah:
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions.
- Yaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma:
Correlation-aware statistical timing analysis with non-gaussian delay distributions.
- Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen:
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model.
- Vishal Khandelwal, Ankur Srivastava:
A general framework for accurate statistical timing analysis considering correlations.
Advances in design-for-testability methods
Advances in boundary element methods for parasitic extraction
- Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram:
A green function-based parasitic extraction method for inhomogeneous substrate layers.
- Xin Hu, Jung Hoon Lee, Jacob White, Luca Daniel:
Analysis of full-wave conductor system impedance over substrate using novel integration techniques.
- Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter:
Spatially distributed 3D circuit models.
- Dipanjan Gope, Indranil Chowdhury, Vikram Jandhyala:
DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structures.
- Rong Jiang, Yi-Hao Chang, Charlie Chung-Ping Chen:
ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction.
Management Day Session
- Naveed A. Sherwani, Susan Lippincott Mack, Alex Alexanian, Premal Buch, Carlo Guardiani, Harold Lehon, Peter Rabkin, Atul Sharan:
- Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong:
Partitioning-based approach to fast on-chip decap budgeting and minimization.
- Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Navigating registers in placement for clock network minimization.
- Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu:
Minimizing peak current via opposite-phase clock tree.
- Haihua Su, David Widiger, Chandramouli V. Kashyap, Frank Liu, Byron Krauter:
A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis.
- Chong Zhao, Yi Zhao, Sujit Dey:
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits.
Physical considerations in high-level synthesis
- Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik:
Temperature-aware resource allocation and binding in high-level synthesis.
- Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee:
Leakage power optimization with dual-Vth library in high-level synthesis.
- Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou:
Incremental exploration of the combined physical and behavioral design space.
- M. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi:
Sign bit reduction encoding for low power applications.
- Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga:
A watermarking system for IP protection by a post layout incremental router.
Architectures for cryptography and security applications
- Kris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede:
A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing.
- Kris Tiri, Ingrid Verbauwhede:
Simulation models for side-channel information leaks.
- Young H. Cho, William H. Mangione-Smith:
A pattern matching coprocessor for network security.
- Tomás Balderas-Contreras, René Cumplido:
High performance encryption cores for 3G networks.
- Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Efficient fingerprint-based user authentication for embedded systems.
and fault-tolerance considerations for MPSoC designs
- Yanhong Liu, Samarjit Chakraborty, Wei Tsang Ooi:
Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC design.
- Christian Sauer, Matthias Gries, Sören Sonntag:
Modular domain-specific implementation and exploration framework for embedded software platforms.
- Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe:
Simulation based deadlock analysis for system level designs.
- Sorin Manolache, Petru Eles, Zebo Peng:
Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC.
- Andrey V. Zykov, Elias Mizan, Margarida F. Jacome, Gustavo de Veciana, Ajay Subramanian:
High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trade-offs.
Management Day Session
losing the power gap between ASIC and custom
information design methodology
- Jean-Samuel Chenard, Chun Yiu Chu, Zeljko Zilic, Milica Popovic:
Design methodology for wireless nodes with printed antennas.
- Yan Meng, Andrew P. Brown, Ronald A. Iltis, Timothy Sherwood, Hua Lee, Ryan Kastner:
MP core: algorithm and design techniques for efficient channel estimation in wireless applications.
- Wolfgang Eberle, Bruno Bougard, Sofie Pollin, Francky Catthoor:
From myth to methodology: cross-layer design for energy-efficient wireless communication.
Statistical optimization and manufacturability
Application specific architecture design tools
- Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Fine-grained application source code profiling for ASIP design.
- Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt:
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration.
- Ho Young Kim, Tag Gon Kim:
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse.
- Dohyung Kim, Youngmin Yi, Soonhoi Ha:
Trace-driven HW/SW cosimulation using virtual synchronization technique.
what went wrong!
Design methods for manufacturability enhancements
- V. Kheterpal, V. Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi:
Design methodology for IC manufacturability based on regular logic-bricks.
- Jie Yang, Luigi Capodieci, Dennis Sylvester:
Advanced timing analysis based on post-OPC extraction of critical dimensions.
- Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester:
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions.
- Joydeep Mitra, Peng Yu, David Zhigang Pan:
RADAR: RET-aware detailed routing using fast lithography simulations.
Methods and representations for logic synthesis
Generating efficient models for analog circuits
emerging directions in wireless
CAD for FPGAs
Effective formal verification using word-level reasoning,
- Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke:
Word level predicate abstraction and refinement for verifying RTL verilog.
- Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer:
Structural search for RTL with predicate learning.
- Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Normalization at the arithmetic bit level.
- Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman:
Exploiting suspected redundancy without proving it.
- Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson:
Advances in synthesis
- Grace Nordin, Peter A. Milder, James C. Hoe, Markus Püschel:
Automatic generation of customized discrete fourier transform IPs.
- Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu:
Race-condition-aware clock skew scheduling.
- Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy:
A novel synthesis approach for active leakage power reduction using dynamic supply gating.
- Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Designing logic circuits for probabilistic computation in the presence of noise.
- Peggy B. McGee, Steven M. Nowick:
A lattice-based framework for the classification and design of asynchronous pipelines.
Coping with buffering
Impact of process variations on power
- Hongliang Chang, Sachin S. Sapatnekar:
Full-chip analysis of leakage power under process variations, including spatial correlations.
- Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm:
Variations-aware low-power design with voltage scaling.
- Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director:
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance.
- Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Leakage minimization of nano-scale circuits in the presence of systematic and random variations.
The best of wireless at ISSCC
- Pascal Urard, L. Paumier, P. Georgelin, T. Michel, V. Lebars, E. Yeo, B. Gupta:
A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3).
- Philippe Royannez, Hugh Mair, Franck Dahan, Mike Wagner, Mark Streeter, Laurent Bouetel, Joel Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, Claudine Raibaut, Uming Ko:
A design platform for 90-nm leakage reduction techniques.
- Arun Natarajan, Abbas Komijani, Ali Hajimiri:
A 24 GHz phased-array transmitter in 0.18µm CMOS.
Architectural support for communication
- Taeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee:
Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs.
- Jongman Kim, Dongkook Park, Theo Theocharides, Narayanan Vijaykrishnan, Chita R. Das:
A low latency router supporting adaptivity for on-chip interconnects.
- Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane:
Floorplan-aware automated synthesis of bus-based communication architectures.
- Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology.
- Sven Heithecker, Rolf Ernst:
Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements.
New approaches to physical design problems
MATLAB - the other emerging system-design language
- David P. Magee:
Matlab extensions for the development, testing and verification of real-time DSP software.
- Tejas M. Bhatt, Dennis McCain:
Matlab as a development environment for FPGA design.
Emerging ideas in energy management techniques
Advances in optimization of mixed-signal circuits
Circuit performance under parameter variation
Formally verifying your 10-million gate design
- Yaron Wolfsthal, Rebecca M. Gott:
Formal verification: is it real enough?
- Umberto Rossi:
Can we really do without the support of formal methods in the verification of large designs?
- Prosenjit Chatterjee:
Streamline verification process with formal property verification to meet highly compressed design cycle.
Embedded hardware and system software
Power estimation and design tradeoffs
- Yan Lin, Lei He:
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction.
- Marvin Tom, Guy G. Lemieux:
Logic block clustering of large designs for channel-width constrained FPGAs.
- Antonio Carlos Schneider Beck, Luigi Carro:
Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility.
cool algorithms and hot applications
DFM and variability:
Theory and practice
- N. S. Nagaraj, Tom Bonifield, Abha Singh, Clive Bittlestone, Usha Narasimha, Viet Le, Anthony M. Hill:
BEOL variability and impact on RC extraction.
- Carlo Guardiani, Massimo Bertoletti, Nicola Dragone, Marco Malcotti, Patrick McNamara:
An effective DFM strategy requires accurate process and IP pre-characterization.
- James Tschanz, Keith A. Bowman, Vivek De:
Variation-tolerant circuits: circuit solutions and techniques.
- Farid N. Najm:
On the need for statistical timing analysis.
- David Blaauw, Kaviraj Chopra:
CAD tools for variation tolerance.
- Matt Nowak, Riko Radojcic:
Are there economic benefits in DFM?
Tools and methods for the verification of processors and processor-based systems
- Allon Adir, Hezi Azatchi, Eyal Bin, Ofer Peled, Kirill Shoikhet:
A generic micro-architectural test plan approach for microprocessor verification.
- Sudheendra Hangal, Naveen Chandra, Sridhar Narayanan, Sandeep Chakravorty:
IODINE: a tool to automatically infer dynamic invariants for hardware designs.
- Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Lichtenstein, Michal Rimon, Michael Vinov, Massimo A. Calligaro, Andrew Cofler, Gabriel Duffy:
VLIW: a case study of parallelism verification.
- Ilya Wagner, Valeria Bertacco, Todd M. Austin:
StressTest: an automatic approach to test generation via activity monitors.
- Sadik Ezer, Scott Johnson:
Smart diagnostics for configurable processor verification.
Electrical optimization for physical synthesis
- Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sherief Reda, Qinke Wang:
- Amit Chowdhary, Karthik Rajagopal, Satish Venkatesan, Tung Cao, Vladimir Tiourin, Yegna Parasuram, Bill Halpin:
How accurately can we model timing in a placement engine?
- Hiran Tennakoon, Carl Sechen:
Efficient and accurate gate sizing with piecewise convex delay models.
- Yuantao Peng, Xun Liu:
Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method.
Optimization techniques in high-level synthesis
Testing for process- and timing-related faults
- Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato:
Path delay test compaction with process variation tolerance.
- Rasit Onur Topaloglu, Alex Orailoglu:
A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs.
- Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies.
- Yannick Monnet, Marc Renaudin, Régis Leveugle:
Asynchronous circuits transient faults sensitivity evaluation.
Hierarchical design and design space exploration of analog integrated circuits
Dynamic voltage scaling
New directions in FPGA technologies
Copyright © Mon Nov 2 20:27:56 2009
by Michael Ley (email@example.com)