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42. DAC 2005: San Diego, CA, USA

William H. Joyner Jr., Grant Martin, Andrew B. Kahng (Eds.): Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005. ACM 2005, ISBN 1-59593-058-2 CiteSeerX Google scholar pubzone.org BibTeX bibliographical record in XML


Error-tolerant design

Microarchitecture-level power analysis and optimization techniques

Leakage analysis and optimization

Analog macromodeling


Statistical timing analysis

Embedded software

Advances in design-for-testability methods

Advances in boundary element methods for parasitic extraction

Management Day Session


Physical considerations in high-level synthesis

Architectures for cryptography and security applications

Performance, energy, and fault-tolerance considerations for MPSoC designs

Management Day Session

losing the power gap between ASIC and custom


Wireless session: information design methodology

Statistical optimization and manufacturability

Application specific architecture design tools

The Titanic: what went wrong!


Design methods for manufacturability enhancements

Methods and representations for logic synthesis

Generating efficient models for analog circuits

Special session: emerging directions in wireless


Effective formal verification using word-level reasoning, bit-level generality, and parallelism

Advances in synthesis

Coping with buffering


Impact of process variations on power

Special session: The best of wireless at ISSCC

Architectural support for communication

New approaches to physical design problems

Special session: MATLAB™ - the other emerging system-design language


Emerging ideas in energy management techniques

Advances in optimization of mixed-signal circuits

Circuit performance under parameter variation

Special session: Formally verifying your 10-million gate design

Embedded hardware and system software

Power estimation and design tradeoffs

Programmable architectures

SAT: cool algorithms and hot applications

Special session: DFM and variability: Theory and practice

Tools and methods for the verification of processors and processor-based systems

Electrical optimization for physical synthesis

Optimization techniques in high-level synthesis

Testing for process- and timing-related faults

Special session: Hierarchical design and design space exploration of analog integrated circuits


Dynamic voltage scaling

New directions in FPGA technologies

Reduced-order modeling

Copyright © Mon Nov 2 20:27:56 2009 by Michael Ley (ley@uni-trier.de)