2. CHES 2000: Worcester, MA, USA

@proceedings{DBLP:conf/ches/2000,
  editor    = {\c{C}etin Kaya Ko\c{c} and
               Christof Paar},
  title     = {Cryptographic Hardware and Embedded Systems - CHES 2000, Second
               International Workshop, Worcester, MA, USA, August 17-18, 2000,
               Proceedings},
  booktitle = {CHES},
  publisher = {Springer},
  series    = {Lecture Notes in Computer Science},
  volume    = {1965},
  year      = {2000},
  isbn      = {3-540-41455-X},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Invited Talk

• Darrel Hankerson, Julio López Hernandez, Alfred Menezes:
  Software Implementation of Elliptic Curve Cryptography over Binary Fields. 1-24
  

Implementation of Elliptic Curve Cryptosystems

• Souichi Okada, Naoya Torii, Kouichi Itoh, Masahiko Takenaka:
  Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2^m) on an FPGA. 25-40
  
• Gerardo Orlando, Christof Paar:
  A High Performance Reconfigurable Elliptic Curve Processor for GF(2^m). 41-56
  
• Jae Wook Chung, Sang Gyoo Sim, Pil Joong Lee:
  Fast Implementation of Elliptic Curve Defined over GF(p^m) on CalmRISC with MAC2424 Coprocessor. 57-70
  

Power and Timing Analysis Attacks

• Adi Shamir:
  Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies. 71-77
  
• Rita Mayer-Sommer:
  Smartly Analyzing the Simplicity and the Power of Simple Power Analysis on Smartcards. 78-92
  
• M. Anwarul Hasan:
  Power Analysis Attacks and Algorithmic Approaches to their Countermeasures for Koblitz Curve Cryptosystems. 93-108
  
• Werner Schindler:
  A Timing Attack against RSA with the Chinese Remainder Theorem. 109-124
  

Hadrware Implementation of Block Cyphers

• Andreas Dandalis, Viktor K. Prasanna, José D. P. Rolim:
  A Comparative Study of Performance of AES Final Candidates Using FPGAs. 125-140
  
• Cameron Patterson:
  A Dynamic FPGA Implementation of the Serpent Block Cipher. 141-155
  
• Steven Trimberger, Raymond Pang, Amit Singh:
  A 12 Gbps DES Encryptor/Decryptor Core in an FPGA. 156-163
  
• Herbert Leitold, Wolfgang Mayerwieser, Udo Payer, Karl C. Posch, Reinhard Posch, Johannes Wolkerstorfer:
  A 155 Mbps Triple-DES Network Encryptor. 164-174
  

Hardware Architectures

• James Goodman, Anantha Chandrakasan:
  An Energy Efficient Reconfigurable Public-Key Cryptograhpy Processor Architecture. 175-190
  
• Johann Großschädl:
  High-Speed RSA Hardware Based on Barret's Modular Reduction Method. 191-203
  
• Colin D. Walter:
  Data Integrity in Hardware for Modular Arithmetic. 204-215
  
• Takehiko Kato, Satoru Ito, Jun Anzai, Natsume Matsuzaki:
  A Design for Modular Exponentiation Coprocessor in Mobile Telecommunication Terminals. 216-228
  

Invited Talk

• David Naccache, Michael Tunstall:
  How to Explain Side-Channel Leakage to Your Kids. 229-230
  

Power Analysis Attacks

• Jean-Sébastien Coron, Louis Goubin:
  On Boolean and Arithmetic Masking against Differential Power Analysis. 231-237
  
• Thomas S. Messerges:
  Using Second-Order Power Analysis to Attack DPA Resistant Software. 238-251
  
• Christophe Clavier, Jean-Sébastien Coron, Nora Dabbous:
  Differential Power Analysis in the Presence of Hardware Countermeasures. 252-263
  

Arithmetic Architectures

• Huapeng Wu:
  Montgomery Multiplier and Squarer in GF(2^m). 264-276
  
• Erkay Savas, Alexandre F. Tenca, Çetin Kaya Koç:
  A Scalable and Unified Multiplier Architecture for Finite Fields GF(p) and GF(2^m). 277-292
  
• Gaël Hachez, Jean-Jacques Quisquater:
  Montgomery Exponentiation with no Final Subtractions: Improved Results. 293-301
  

Physical Security and Cryptanalysis

• Steve H. Weingart:
  Physical Security Devices for Computer Subsystems: A Survey of Attacks and Defences. 302-317
  
• Thomas Pornin, Jacques Stern:
  Software-Hardware Trade-Offs: Application to A5/1 Cryptanalysis. 318-327
  

New Schemes and Algorithms

• Jeffrey Hoffstein, Joseph H. Silverman:
  MiniPASS: Authentication and Digital Signatures in a Constrained Environment. 328-339
  
• Marc Joye, Pascal Paillier, Serge Vaudenay:
  Efficient Generation of Prime Numbers. 340-354