5. Conference On Computing Frontiers 2009: Ischia, Italy

Innovative memory systems

• Magnus Jahre, Lasse Natvig:
  A light-weight fairness mechanism for chip multiprocessor memory systems. 1-10
  
• Salil Mohan Pant, Gregory T. Byrd:
  Extending concurrency of transactional memory programs by using value prediction. 11-20
  
• Shaoshan Liu, Ligang Wang, Xiao-Feng Li, Jean-Luc Gaudiot:
  Space-and-time efficient garbage collectors for parallel systems. 21-30
  

Advanced architecture 1

• Paul E. West, Yuval Peress, Gary S. Tyson, Sally A. McKee:
  Core monitors: monitoring performance in multicore processors. 31-40
  
• Kai Tian, Yunlian Jiang, Xipeng Shen:
  A study on optimally co-scheduling jobs of different lengths on chip multiprocessors. 41-50
  
• Jih-Ching Chiu, Yu-Liang Chou, Hua-Yi Tzeng:
  A multi-streaming SIMD architecture for multimedia applications. 51-60
  

HPC applications

• Friman Sánchez, Alex Ramírez, Mateo Valero:
  Quantitative analysis of sequence alignment applications on multiprocessor architectures. 61-70
  
• Ioannis E. Venetis, Guang R. Gao:
  Mapping the LU decomposition on a many-core architecture: challenges and solutions. 71-80
  
• Simona Caraiman, Vasile I. Manta:
  New applications of quantum algorithms to computer graphics: the quantum random sample consensus algorithm. 81-88
  

Novel tools and methods 1

• Sean Rul, Hans Vandierendonck, Koen De Bosschere:
  Towards automatic program partitioning. 89-98
  
• Hongyang Sun, Yangjie Cao, Wen-Jing Hsu:
  Non-clairvoyant speed scaling for batched parallel jobs on multiprocessors. 99-108
  
• Konstantinos I. Karantasis, Eleftherios D. Polychronopoulos:
  Pleiad: a cross-environment middleware providing efficient multithreading on clusters. 109-116
  

Innovative acceleration platforms

• Pedro Trancoso, Despo Othonos, Artemakis Artemiou:
  Data parallel acceleration of decision support queries using Cell/BE and GPUs. 117-126
  
• Dimitris Theodoropoulos, Catalin Bogdan Ciobanu, Georgi Kuzmanov:
  Wave field synthesis for 3D audio: architectural prospectives. 127-136
  
• Maryam Moazeni, Alex A. T. Bui, Majid Sarrafzadeh:
  Accelerating total variation regularization for matrix-valued images on GPUs. 137-146
  
• Snaider Carrillo, Jakob Siegel, Xiaoming Li:
  A control-structure splitting optimization for GPGPU. 147-150
  

Advanved architectures 2

• Tameesh Suri, Aneesh Aggarwal:
  Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration. 151-160
  
• Filip Blagojevic, Costin Iancu, Katherine A. Yelick, Matthew Curtis-Maury, Dimitrios S. Nikolopoulos, Benjamin Rose:
  Scheduling dynamic parallelism on accelerators. 161-170
  
• Dominic A. Antonelli, Alan Jay Smith, Jan-Willem van de Waerdt:
  Power consumption and reduction in a real, commercial multimedia core. 171-174
  

Novel tools and methods 2

• Jay L. T. Cornwall, Lee W. Howes, Paul H. J. Kelly, Phil Parsonage, Bruno Nicoletti:
  High-performance SIMT code generation in an active visual effects library. 175-184
  
• John P. Karidis, José E. Moreira, Jaime H. Moreno:
  True value: assessing and optimizing the cost of computing at the data center level. 185-192
  
• Thomas Hérault, Thomas Largillier, Sylvain Peyronnet, Benjamin Quétier, Franck Cappello, Mathieu Jan:
  High accuracy failure injection in parallel and distributed systems using virtualization. 193-196
  

Advanced computing systems management and evaluation

• Oreste Villa, Sriram Krishnamoorthy, Jarek Nieplocha, David M. Brown Jr.:
  Scalable transparent checkpoint-restart of global address space applications on virtual machines over infiniband. 197-206
  
• Alexander S. van Amesfoort, Ana Lucia Varbanescu, Henk J. Sips, Rob van Nieuwpoort:
  Evaluating multi-core platforms for HPC data-intensive kernels. 207-216
  
• Peter Bertels, Wim Heirman, Dirk Stroobandt:
  Strategies for dynamic memory allocation in hybrid architectures. 217-220
  
• Harmen L. A. van der Spek, Erwin M. Bakker, Harry A. G. Wijshoff:
  Characterizing the performance penalties induced by irregular code using pointer structures and indirection arrays on the intel core 2 architecture. 221-224
  
• Ronny Ronny Ronen:
  Larrabee: a many-core Intel architecture for visual computing. 225
  
• Michael Shebanow:
  Pervasive massively multithreaded GPU processors. 227